Shift Register Circuit for Sequential Low- and High-Level Output
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Solution Overview
Problem
Existing shift register circuits using n-channel transistors struggle to output low-level signals sequentially, while those using p-channel transistors struggle to output high-level signals sequentially, and both face challenges in reducing circuit scale and power consumption.
Innovation Solution
A semiconductor device with a specific configuration of transistors and switches that allows for sequential output of low-level signals using n-channel transistors and high-level signals using p-channel transistors, while minimizing circuit scale and power consumption, by connecting transistors with oxide semiconductor channels and incorporating switches to control signal flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a shift register circuit uses n-channel transistors to output clock signals at high level, then high-level signals can be output sequentially, but low-level signals cannot be output sequentially
Solution Approach 1:
The patent inverts the conventional approach by using n-channel transistors to output low-level signals instead of high-level signals. The shift register circuit is designed to output low-level clock signals sequentially, reversing the traditional behavior where n-channel transistors output high-level signals. This inversion resolves the limitation by enabling the circuit to output the previously unachievable low-level signals while maintaining sequential output capability.
2Ease of operation
If a shift register circuit uses p-channel transistors to output clock signals at low level, then low-level signals can be output sequentially, but high-level signals cannot be output sequentially
Solution Approach 1:
The patent inverts the conventional approach by using p-channel transistors to output high-level signals instead of low-level signals. The shift register circuit is designed to output high-level clock signals sequentially, reversing the traditional behavior where p-channel transistors output low-level signals. This inversion resolves the limitation by enabling the circuit to output the previously unachievable high-level signals while maintaining sequential output capability.
3Adaptability or versatility
If the circuit configuration is expanded to output both high-level and low-level signals sequentially, then signal versatility is improved, but circuit scale increases
Solution Approach 1:
The patent makes the shift register circuit universal by enabling it to output both high-level and low-level signals sequentially using a single circuit configuration. By designing the circuit to accept control signals that determine the output level, the same circuit can function as either an high-level or low-level signal output circuit, eliminating the need for separate circuits for each signal type and thereby reducing overall circuit scale.
4Adaptability or versatility
If the circuit configuration is expanded to output both high-level and low-level signals sequentially, then signal versatility is improved, but power consumption increases
Solution Approach 1:
The patent makes the shift register circuit universal by enabling it to output both high-level and low-level signals sequentially using a single circuit configuration. By designing the circuit to accept control signals that determine the output level, the same circuit can function as either an high-level or low-level signal output circuit, eliminating the need for separate circuits for each signal type and thereby reducing overall power consumption.
Data Source
AI summary
A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.