Shift Register Single Clock Signal Narrow Frame Display
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Solution Overview
Problem
The use of multiple clock signal lines in shift registers for display panels increases wiring difficulty and occupies more space, contradicting the design requirements for a narrow frame display panel.
Innovation Solution
A shift register design comprising an input circuit, reset circuit, pull-down control circuit, and output circuit, which allows normal shift output under the control of a single clock signal terminal, reducing the number of clock signal lines needed and minimizing space occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock signal lines are used in shift registers, then the shift register can operate reliably, but the wiring complexity and space occupation increase
Solution Approach 1:
The patent merges multiple clock signal lines into a single clock signal line by using a pull-down control circuit that generates multiple internal clock signals from one external clock signal. This reduces wiring complexity while maintaining the reliability of shift register operation through the generated multiple internal clock phases.
Solution Approach 2:
The pull-down control circuit acts as an intermediary between the single external clock signal line and the multiple internal clock signal requirements. It generates the necessary multiple clock phases internally, eliminating the need for multiple external clock signal lines while ensuring reliable operation.
2Reliability
If multiple clock signal lines are used in shift registers, then the shift register can operate reliably, but the space occupation increases
Solution Approach 1:
The patent merges multiple clock signal lines into a single clock signal line by using a pull-down control circuit that generates multiple internal clock signals from one external clock signal. This reduces wiring complexity while maintaining the reliability of shift register operation through the generated multiple internal clock phases.
Solution Approach 2:
The patent transitions from using multiple external clock signal lines (spatial dimension) to generating multiple internal clock phases temporally from a single external clock signal. This dimensional change from spatial multiplicity to temporal multiplicity reduces the area occupied by clock signal wiring.
3Device complexity
If a single clock signal line is used, then wiring complexity and space occupation are reduced, but the shift register cannot generate multiple clock phases
Solution Approach 1:
The pull-down control circuit acts as an intermediary between the single external clock signal line and the multiple internal clock signal requirements. It generates the necessary multiple clock phases internally, eliminating the need for multiple external clock signal lines while ensuring reliable operation.
Solution Approach 2:
The shift register circuit generates its own multiple internal clock phases from a single external clock signal through the pull-down control circuit. This self-service capability eliminates the need for external multiple clock signal lines while maintaining full operational capability.
Data Source
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AI summary
This application discloses a shift register, a gate drive circuit and a display device. The signal of the input signal terminal is provided to the pull-up node by the input circuit under the control of the input signal terminal; and the signal of the second reference signal terminal is provided to the output signal terminal by the output circuit under the control of the clock signal terminal and the signal of the pull-up node. The signal of the first reference signal terminal is provided to the pull-up node by the reset circuit under the control of the input signal terminal and the clock signal terminal. The pull-down control circuit resets the output signal terminal according to the signal of the first reference signal terminal.