Shift Register Gate Driving Circuit Noise Reduction
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Solution Overview
Problem
Conventional display panel gate driving circuits face challenges in reducing manufacturing costs and complexity, particularly due to the need for multiple DC signals and interference between signal and reset signals during the input phase, which complicates the circuit structure and increases noise.
Innovation Solution
A shift register design incorporating an input sub-circuit, output sub-circuit, reset control sub-circuit, pull-up node reset sub-circuit, and output signal reset sub-circuit, with a single DC low-level signal, that prevents the pull-up node reset sub-circuit from being turned on during the input phase, thereby reducing noise and simplifying the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple DC signals are used in the gate driving circuit, then the functionality and reliability are improved, but the circuit structure complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple DC signal functions into a single DC low-level signal. The reset control sub-circuit uses this single signal to control both the pull-up node reset sub-circuit and the output signal reset sub-circuit, eliminating the need for multiple separate DC signals while maintaining all necessary reset functions across the shift register stages.
Solution Approach 2:
The single DC low-level signal serves multiple functions simultaneously: it controls the reset operation of the pull-up node, controls the reset of the output signal, and enables the reset control sub-circuit to manage multiple shift register stages. This multi-functional approach reduces circuit complexity while preserving reliability.
2Reliability
If the pull-up node reset sub-circuit is always active, then the reset function is reliable, but noise interference increases during the input phase
Solution Approach 1:
The patent makes the pull-up node reset sub-circuit dynamic by controlling its activation state through the reset control sub-circuit. The sub-circuit is activated only when needed (during reset phases) and remains inactive during the input phase, allowing the circuit to adapt its behavior to different operational requirements and eliminate unnecessary noise.
Solution Approach 2:
The reset control sub-circuit enables periodic activation of the pull-up node reset sub-circuit based on the driving phase. The sub-circuit operates during specific reset phases and remains dormant during input phases, creating a periodic action pattern that ensures reliable resetting when needed while preventing noise interference during other operations.
3Device complexity
If a single DC low-level signal is used, then the circuit structure is simplified and manufacturing cost is reduced, but the ability to control multiple functions independently is limited
Solution Approach 1:
The reset control sub-circuit acts as an intermediary between the single DC low-level signal and the multiple reset functions. It receives the single signal and distributes/controls it to appropriate sub-circuits (pull-up node reset sub-circuit and output signal reset sub-circuit) at appropriate times, enabling one signal to effectively control multiple functions with timing differentiation.
Solution Approach 2:
The patent applies different control characteristics to different parts of the circuit using the single DC signal. The reset control sub-circuit differentiates between when to activate the pull-up node reset sub-circuit versus when to activate the output signal reset sub-circuit, giving each part the appropriate local control quality it needs while using a unified signal source.
Data Source
AI summary
The present application discloses a shift register, a gate driving circuit and a driving method thereof, and a display apparatus. The shift register includes an input sub-circuit, an output sub-circuit, a reset control sub-circuit, a pull-up node reset sub-circuit, and an output signal reset sub-circuit; the input sub-circuit is configured to pre-charge the pull-up node under the control of a signal input to the first signal input terminal; the output sub-circuit is configured to output, through the signal output terminal, a signal input to the first clock signal input terminal under the control of a potential of the pull-up node; the reset control sub-circuit is configured to control, under the control of a reset signal input to the second signal input terminal, whether the pull-up node reset sub-circuit and the output signal reset sub-circuit operate to reset the pull-up node and the signal output terminal, respectively.