Shift Register Stabilization Node Control for Display Reliability
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Solution Overview
Problem
Conventional shift register configurations for driving gate bus lines in liquid crystal display devices face reliability issues due to threshold shifts in transistors, leading to potential fluctuations in output signal levels during normal operation periods, which can cause abnormal operation and increased power consumption.
Innovation Solution
A shift register design incorporating multiple clock phases with an on-duty cycle of less than ½, featuring a stabilization node control portion that maintains the stabilization node at an on level for less than 50% of the operation period, and utilizing thin film transistors with an oxide semiconductor layer to stabilize the output control node and prevent threshold shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the stabilization node is maintained at an on level for a long period, then the output control node can be stabilized, but threshold shifts occur in transistors leading to output signal fluctuations
Solution Approach 1:
The patent applies periodic action by controlling the stabilization node to switch between on and off states in a periodic manner during normal operation. The stabilization node is set to on level for a controlled duration less than 50% of the operation period, then switched off, preventing continuous conduction that causes threshold shifts while still periodically stabilizing the output control node to prevent abnormal operation and reduce power consumption.
2Use of energy by moving object
If multiple clock phases are used with reduced on-duty cycle, then power consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent segments the clock signal into multiple phases (at least three phases: first, second, and third clock signals) with different timing relationships. Each clock phase controls specific transistors in the unit circuit at different time intervals, allowing the circuit to operate with reduced on-duty cycle for each phase while maintaining overall functionality. This segmentation reduces power consumption by ensuring not all transistors conduct simultaneously, though it increases circuit complexity through multiple clock input terminals and phase control logic.
Data Source
AI summary
A shift register is implemented that can increase the reliability of long-term operation regarding the driving of gate bus lines over a conventional configuration. The shift register is allowed to operate by clock signals of eight or more phases with an on-duty of less than ½. A stabilization node control portion brings a stabilization node (NB) to an on level for a period less than 50 percent of a normal operation period, based on two or more clock signals among the clock signals of eight or more phases, the stabilization node (NB) being connected to a gate terminal of a thin film transistor that contributes to the drawing of a potential of an output control node (NA) to a VSS potential.