Shift Register Stabilization Switching Device for Charge Leakage
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Solution Overview
Problem
Shift registers in display devices face issues with charge leakage at set nodes due to low duty ratios of scan pulses, leading to unstable output of scan pulses.
Innovation Solution
The design incorporates a shift register with carry output switching devices, scan output switching devices, and stabilization switching devices, where the stabilization switching device is controlled by overlapping carry and scan clock pulses to maintain node voltage during low duration periods, preventing charge leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the duty ratio of the scan pulse is reduced, then the low duration is extended, but charge leakage at the set node increases
Solution Approach 1:
The stabilization switching device is activated before the low duration begins (controlled by overlapping carry and scan clock pulses) to preemptively prevent charge leakage at the set node during the extended low duration period
Solution Approach 2:
The stabilization switching device acts as an intermediary element that mediates between the scan output switching device and the set node, preventing charge leakage without interfering with the normal scan pulse output function
2Duration of action of moving object
If the duty ratio of the scan pulse is reduced, then the low duration is extended, but the scan pulse output becomes unstable
Solution Approach 1:
The stabilization switching device is activated in advance (controlled by overlapping clock pulses) to prevent voltage drop at the set node before it occurs, ensuring stable scan pulse output during the extended low duration
Solution Approach 2:
The stabilization switching device provides beforehand cushioning by maintaining the set node voltage during the low duration, preventing instability in the scan pulse output that would otherwise occur with extended low duration periods
Data Source
AI summary
A shift register includes a plurality of stages, each of which outputs a carry pulse and a scan pulse. An nth one of the stages includes a carry output switching device controlled by a voltage applied to a set node and connected between a carry clock transfer line transferring any one of i carry clock pulses and a carry output terminal of the nth stage, a scan output switching device controlled by the voltage applied to the set node and connected between a scan clock transfer line transferring any one of j scan clock pulses and a scan output terminal of the nth stage, and a stabilization switching device controlled by any one of the i carry clock pulses and connected between a carry output terminal of an (n−p)th one of the stages and the set node or between a start transfer line and the set node.


