Shift Register Unit Stabilizing Gate Driving Signal
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Solution Overview
Problem
The existing 4T1C shift register units in display technology suffer from poor stability of gate driving signals due to coupling effects between the gate and source/drain electrodes of thin film transistors, leading to signal jitter during invalid periods.
Innovation Solution
A shift register unit comprising a driving circuit, output circuit, reset circuit, and storage capacitor circuit, with specific transistor connections and control signals to stabilize the gate driving signal, reducing the need for additional TFTs and enhancing signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a 4T1C shift register unit structure is used, then the basic structure is simple, but the gate driving signal stability is poor due to coupling effects causing jitter during invalid periods
Solution Approach 1:
The patent divides the shift register unit into distinct functional modules: a driving circuit with first and second driving transistors, an output circuit with first and second output transistors, a reset circuit with first and second reset transistors, and a storage capacitor circuit. This segmentation allows independent optimization of each module to eliminate coupling effects while maintaining overall simplicity.
Solution Approach 2:
The patent introduces a storage capacitor circuit connected between the pull-up node and the gate driving signal output end as an intermediary element. This capacitor stabilizes the output signal by maintaining voltage during invalid periods, effectively decoupling the output from clock signal fluctuations and eliminating jitter without significantly increasing device complexity.
2Reliability
If additional TFTs are added to improve signal stability, then gate driving signal quality improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs transistors with multi-functional capabilities. For example, the first driving transistor controls both the pull-up node connection to set signal input and the overall driving function, while the second driving transistor handles pull-down operations. This multi-functionality reduces the total transistor count needed to achieve stable signal output.
Solution Approach 2:
The patent combines the driving, output, and reset functions into a unified 6-transistor architecture where transistors work in coordinated pairs. The first and second driving transistors operate together with the storage capacitor, while the first and second output transistors collectively control the gate driving signal output. This merging achieves signal stability without requiring excessive individual components.
3Productivity
If the gate electrode is continuously connected to clock signal input, then the shift register operates continuously, but coupling effects cause dither of all gate drive signal outputs
Solution Approach 1:
The patent implements periodic control of the gate driving signal through phased clock inputs. The first and second driving transistors receive clock signals with different phases, creating periodic switching actions that drive the pull-up and pull-down nodes in sequence. This periodic operation maintains continuous productivity while the storage capacitor filters out high-frequency jitter components.
Solution Approach 2:
The storage capacitor circuit provides feedback stabilization to the gate driving signal output. By maintaining the voltage level during transitions and invalid periods, the capacitor creates a feedback effect that counteracts coupling-induced jitter, ensuring stable signal output throughout continuous operation without interrupting productivity.
Data Source
AI summary
A shift register unit, a method for driving the same, a gate driving circuit, and a display device are provided. The shift register unit includes a driving circuit, a storage capacitor circuit, an output circuit, and a reset circuit. Under the control of the start end, the driving circuit controls whether the pull-up node is connected to the set signal input end and control whether the pull-down node is connected to the first level input end. Under the control of the reset end, the reset circuit controls whether the pull-up node is connected to the first level input end, and controls whether the pull-down node is connected to the second level input end.