Shift Register Circuit Stabilizing Output Voltage
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Solution Overview
Problem
Conventional shift register circuits lack a design for stably controlling driving voltage, affecting the stability of output signals in gate drivers used in display panels.
Innovation Solution
A shift register circuit design that includes an input circuit, a driving circuit, and a pull-down circuit, which adjusts node voltages using interlaced clock signals to stabilize output voltages, ensuring stable low-voltage output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional shift register circuit is used, then the circuit structure is simple, but the output voltage stability is poor
Solution Approach 1:
The shift register circuit is divided into three functional modules: input circuit (including first and second input transistors), driving circuit (including third and fourth input transistors, and first and second output transistors), and pull-down circuit (including fifth and sixth input transistors, and third and fourth output transistors). This segmentation allows each module to perform specific voltage control functions, improving output stability while maintaining reasonable circuit complexity.
Solution Approach 2:
The circuit uses interlaced clock signals to pre-charge nodes to appropriate voltage levels before data transmission. The pull-down circuit proactively pulls nodes to low voltage levels when needed, preventing voltage instability before it occurs. This preliminary action ensures that nodes are always in the correct voltage state for reliable operation.
2Reliability
If voltage control is not implemented, then the circuit operation is simple, but erroneous signals occur
Solution Approach 1:
The circuit employs interlaced clock signals that provide feedback control over node voltages. The clock signals are generated based on the operational state of the shift register, creating a feedback mechanism that continuously adjusts voltages to maintain signal accuracy and prevent erroneous outputs.
Solution Approach 2:
The circuit dynamically changes voltage parameters at different nodes using the interlaced clock signals. By controlling the timing and level of voltages applied to different nodes, the circuit ensures accurate signal transmission while preventing erroneous outputs, without requiring overly complex control mechanisms.
Data Source
AI summary
A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.


