Shift Register Stage Reduction in Pipeline Circuits
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Solution Overview
Problem
In the design of semiconductor devices, pipeline circuits with multiple stages face inefficiencies due to unnecessary copying of values across stages, leading to complex shift register structures that require optimization to reduce the number of stages without affecting operational equivalence.
Innovation Solution
A circuit description generation apparatus that extracts shift register groups, generates waveforms based on input signal patterns, and identifies candidates for reducing the number of stages by analyzing cycles until signal changes, then verifies operational equivalence after reducing the number of stages in the shift register groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same value is copied to pipeline registers over multiple stages to ensure data availability, then reliability of data transmission is improved, but device complexity increases due to unnecessary shift register stages
Solution Approach 1:
The invention extracts and eliminates unnecessary shift register stages from the pipeline circuit. By analyzing data flow patterns and identifying stages where data is merely copied without transformation, the method removes these redundant registers, thereby reducing device complexity while preserving the reliability of essential data transmission paths.
Solution Approach 2:
The invention changes the parameter of shift register stage count by dynamically determining the minimum necessary stages based on actual data flow requirements. Instead of using a fixed or over-provisioned number of stages, the method adjusts the stage count parameter to match the actual computational needs, reducing complexity without compromising reliability.
2Productivity
If multiple pipeline stages are used to process operations in parallel, then productivity is improved, but device complexity increases due to additional shift registers
Solution Approach 1:
The invention extracts and removes redundant shift register stages that do not contribute to actual computational progress. By identifying and eliminating these unnecessary stages, the method reduces the total number of registers while maintaining the parallel processing capability and throughput efficiency of the pipeline circuit.
Solution Approach 2:
The invention applies partial action by implementing only the necessary number of pipeline stages required for actual computation, rather than using excessive stages. This approach maintains sufficient parallel processing capability for high productivity while avoiding the complexity overhead of unnecessary additional registers.
3Device complexity
If shift register stages are reduced to simplify the circuit, then device complexity is reduced, but reliability may deteriorate due to insufficient data staging
Solution Approach 1:
The invention uses feedback mechanisms to verify that reducing shift register stages does not compromise operational equivalence. By simulating and analyzing data flow through the reduced pipeline stages, the method ensures that essential data transmission and computational requirements are still met, thereby maintaining reliability while achieving complexity reduction.
Solution Approach 2:
The invention performs preliminary analysis of data flow patterns and computational requirements before finalizing the reduced shift register configuration. This advance planning ensures that the reduced structure will maintain operational equivalence and reliability by identifying which stages are essential and which can be safely removed.
Data Source
AI summary
According to one embodiment, a circuit description generation apparatus includes: a reduction candidate extraction unit that generates a waveform of an input signal based on a verification vector, and extracts a candidate for reducing the number of stages of shift registers, based on a minimum value of the number of cycles that last until a change in a value of a signal represented by the waveform; and a reduction circuit generation unit that generates circuit information describing a circuit in which the reduction has been made, and verifies whether or not there is equivalence in output between a circuit before the reduction and a circuit after the reduction.