Shift Register Stage Segmentation for Display Panel Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing shift registers in display devices are prone to erroneous operations if any stage is abnormally operated, and decoders, while offering a solution, require a large number of input signals, making them impractical for large display panels or sensors.
Innovation Solution
A shift register design that uses two clock signals and a start signal to stabilize operations across stages, employing transistors and a bootstrap capacitor to maintain and reset voltages, allowing each stage to operate independently and reduce the impact of abnormal stages without increasing the number of input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a decoder is used to prevent erroneous operations in shift register stages, then reliability is improved, but the number of input signals increases significantly making it impractical for large display panels
Solution Approach 1:
The shift register is divided into multiple independent stages, each stage being able to operate autonomously. Each stage includes its own transistor configuration that can function independently, allowing the system to maintain reliability without requiring a decoder for each stage. This segmentation enables local operation while reducing overall system complexity.
Solution Approach 2:
The invention changes the operational parameters of the shift register stages by using specific transistor configurations with controlled voltage levels. By adjusting voltage parameters and transistor switching states, each stage can operate reliably without requiring additional input signals from a decoder, thus maintaining reliability while reducing signal complexity.
2Device complexity
If traditional shift register stages are used, then the number of input signals remains low, but erroneous operations propagate to all subsequent stages when one stage fails
Solution Approach 1:
Each shift register stage is segmented as an independent operational unit with its own transistor configuration. This segmentation ensures that errors in one stage do not propagate to other stages, as each stage can reset or operate independently. The low complexity is maintained by using simple transistor-based isolation rather than complex error correction circuits.
Solution Approach 2:
The transistor configuration in each stage includes built-in protection mechanisms that prevent error propagation before it can occur. By designing each stage with independent voltage control and transistor switching, the system cushions against potential errors from adjacent stages, ensuring that a failure in one stage does not affect others.
3Area of stationary object
If the area of sensor or display panel increases, then more stages are required, but decoder becomes inappropriate due to large number of input signals needed
Solution Approach 1:
The shift register is designed as a scalable segmented structure where each stage is an independent module. This allows the display panel area to be increased by simply adding more stages without increasing the complexity of control signals. Each stage operates autonomously, so the number of input signals remains constant regardless of the number of stages.
Solution Approach 2:
Each shift register stage is designed as a universal module that can be replicated across the entire display panel. The same transistor configuration and operational principles apply to each stage, allowing the system to scale to large display areas without requiring different circuit designs or additional control signals for each stage.
Data Source
AI summary
The present invention relates to a shift register configured of a plurality of stages applying two clock signals among four clock signals that are sequentially generated as an input and applying a start signal as the input, wherein a first stage charges the start signal to a P-node and outputs a first output signal and a first carry signal by using the voltage of the P-node as a driving voltage when a first clock signal is applied, and resets the P-node when a second clock signal is applied, a second stage pre-charges a start signal input to the first stage to the P-node, charges the first carry signal to the P-node, outputs a second output signal and a second carry signal by using the voltage of the P-node as the driving voltage when the second clock signal is applied, and resets the P-node when a third clock signal is applied, and a third stage and following stages pre-charge a carry signal of the second previous stage to the P-node, charge the carry signal of the previous stage to the P-node, output the output signal and the carry signal by using the voltage of the P-node as the driving voltage when the input clock signal secondly input to the P-node is input, and reset the P-node that is charged depending on the clock signal generated after the input clock signal.