Shift Register Stages for LCD Parasitic Capacitance
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Solution Overview
Problem
Current shift registers in small and medium-sized LCDs face issues with parasitic capacitance affecting low voltage driving, leading to errors and transistor malfunction due to increased threshold voltage over time.
Innovation Solution
A shift register design with stages that include input, first, and output units, utilizing diodes and switching elements to synchronize clock signals and generate output signals, minimizing the impact of parasitic capacitance by charging a capacitor with a voltage difference between clock signals, thereby stabilizing gate line voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are made of amorphous silicate and maintained in turned-on state to generate gate output, then gate line voltages are maintained at low voltage, but threshold voltage of transistors increases causing malfunction
Solution Approach 1:
The patent applies periodic action by using multiple clock signals with different phases (CLK1, CLK2, CLK3) to periodically update transistor states. Instead of keeping transistors continuously on, the circuit uses phased clock signals to periodically refresh the gate output while maintaining low voltage levels, thereby preventing threshold voltage drift that occurs with continuous conduction.
Solution Approach 2:
The patent changes operational parameters by introducing multiple clock phases and using capacitor coupling to transfer signals between stages. This parameter change allows the circuit to maintain low gate line voltages without requiring transistors to remain in a constant on-state, thus preventing threshold voltage increase while ensuring reliable operation.
2Reliability
If seven transistors are used to alleviate threshold voltage increase, then transistor malfunction is reduced, but parasitic capacitance between gate line and common electrode causes voltage changes leading to errors
Solution Approach 1:
The patent introduces capacitors as intermediary elements to couple signal stages and transfer clock signals. These capacitors act as mediators that isolate the gate line from direct parasitic capacitance coupling with the common electrode, thereby reducing the harmful voltage changes caused by parasitic effects while maintaining signal integrity.
Solution Approach 2:
The patent replaces direct electrical connection mechanisms with capacitor-based coupling and clock signal phasing. This substitution eliminates the direct path for parasitic capacitance to affect gate line voltages, using electromagnetic field coupling through capacitors instead of direct conductive paths, thereby reducing errors from parasitic effects.
3Use of energy by moving object
If low voltage driving is performed in medium and small sized display devices, then power consumption is reduced, but errors are pronounced due to parasitic capacitance effects
Solution Approach 1:
The patent uses periodic clock signals with phased timing to periodically refresh and maintain signal levels at low voltage. This periodic action ensures that signals are actively maintained at correct levels despite parasitic capacitance, enabling accurate low-voltage driving without the errors that would otherwise occur.
Solution Approach 2:
The patent changes the voltage and timing parameters by using multiple clock phases and capacitor coupling to maintain signal integrity at low voltage levels. This parameter optimization allows accurate signal transmission despite parasitic capacitance effects, enabling precise low-voltage driving for reduced power consumption.
Data Source
AI summary
A shift register and a display device having the shift register are provided. The shift register has a plurality of stages which sequentially generate output signals in synchronization with a plurality of clock signals. Each of the stages includes an input unit for receiving a scan start signal or an output signal from a previous stage and outputting the scan start signal or the output signal as a first voltage, a first unit for passing at least two clock signals, a second unit for outputting at least one of the at least two clock signals or a second voltage in response to an output signal from a next stage, and an output unit for generating an output signal synchronized with at least one of the at least two clock signals in response to the outputs of the input unit and the second unit.