Shift Register Start Pulse Independence
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Solution Overview
Problem
Existing liquid crystal display (LCD) devices require synchronization between the start pulse and clock signal in shift registers, limiting their ability to provide gate driving pulses efficiently, which is a constraint in achieving high-quality picture display with large-sized screens while maintaining thinness, lightness, and low power consumption.
Innovation Solution
A shift register design that includes additional PMOS transistors allowing the start pulse to be supplied independently of clock signal synchronization, ensuring gate driving pulses are outputted even if the clock signal is not synchronized with the start pulse, thereby eliminating the need for synchronization between the two.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronization between start pulse and clock signal is required in shift register, then gate driving pulses can be outputted reliably, but the device complexity and operational constraints increase
Solution Approach 1:
The patent introduces a start pulse signal as an intermediary that can independently trigger the gate driving pulse output without requiring synchronization with the clock signal. The start pulse acts as a mediator that initiates the scanning operation, while the clock signal continues to control the sequential progression of stages. This separates the initiation function from the timing function, eliminating the synchronization constraint while maintaining reliable operation.
2Adaptability or versatility
If additional switching devices are added to eliminate synchronization requirement, then operational flexibility improves, but device complexity increases
Solution Approach 1:
The patent segments the control functions into separate components: the start pulse signal handles the initiation function while the clock signal handles the timing function. By dividing these functions, the system gains flexibility without requiring a complete redesign of the control architecture. The additional switching devices are introduced only where needed to implement this segmentation, rather than throughout the entire system.
3Ease of operation
If start pulse and clock signal are not synchronized, then ease of operation improves, but reliability of pulse output may deteriorate
Solution Approach 1:
The patent applies preliminary action by ensuring that the start pulse is applied before the clock signal begins its sequential operation. This preliminary triggering establishes the initial state of the shift register stages, ensuring that when the clock signal subsequently drives the sequential progression, each stage is properly initialized. This preliminary setup guarantees reliable pulse output even without ongoing synchronization requirements.
Data Source
AI summary
A shift register is provided that outputs a gate driving pulse even if a start pulse provided to a first stage is not synchronized with a clock pulse. The shift register has multiple stages that sequentially output gate driving pulses. At least one stage includes a first switching device turned-on by a first clock signal and applying the start pulse to a first node. A second switching device is turned-on by the first clock signal and applies a first supply voltage to a second node. A third switching device is turned-on by the start pulse applied to the first node and outputs a second clock signal. A fourth switching device is turned-on by the first supply voltage and outputs a second supply voltage. A fifth switching device is turned-on by the start pulse and applies the start pulse to the first node.