Shift Register Sub-Circuit Design for Display Signal Accuracy
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Solution Overview
Problem
Current self-luminous display technologies face challenges in efficiently driving light-emitting devices due to complex circuitry and high manufacturing costs, particularly in providing accurate enable signals to pixel driving circuits in a manner that minimizes power consumption and signal accuracy.
Innovation Solution
A shift register design incorporating input, control, output, and reset sub-circuits, along with a denoising sub-circuit, that transmits and manages voltage signals to control the enable signal output, ensuring accurate and efficient light emission in self-luminous display apparatuses by simplifying the circuit structure and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complex circuit structure is used to drive light-emitting devices, then signal accuracy can be maintained, but manufacturing cost and device complexity increase
Solution Approach 1:
The shift register circuit is divided into multiple sub-circuits (input sub-circuit, control sub-circuit, output sub-circuit, reset sub-circuit) that perform specific functions independently. This segmentation allows each sub-circuit to be optimized for its specific task while maintaining overall signal accuracy, reducing the complexity of any single sub-circuit component.
Solution Approach 2:
The shift register circuit is designed to perform multiple functions (signal transmission, clock distribution, reset operations, noise filtering) within a unified structure. The cascaded configuration allows the same basic circuit topology to be replicated and connected, providing universal functionality across multiple stages without proportionally increasing overall complexity.
2Measurement precision
If more sub-circuits are added to improve signal transmission, then enable signal accuracy improves, but power consumption increases
Solution Approach 1:
The shift register operates in periodic cycles with distinct phases (input phase, clock phase, output phase, reset phase). Each sub-circuit is activated only during its required phase rather than continuously, significantly reducing power consumption while maintaining signal accuracy through timely periodic operation.
Solution Approach 2:
The denoising sub-circuit extracts and removes noise components from the signal path, improving enable signal accuracy without requiring additional complex amplification or regeneration circuits that would consume more power. By extracting only the necessary signal components and filtering out noise, power efficiency is maintained.
3Ease of manufacture
If a simplified circuit structure is used, then manufacturing cost decreases, but signal transmission accuracy deteriorates
Solution Approach 1:
By segmenting the circuit into standardized sub-circuits with well-defined interfaces, the design achieves simplicity in individual components while maintaining overall accuracy through the coordinated operation of segments. This modular approach reduces manufacturing complexity compared to a monolithic complex circuit.
Solution Approach 2:
The control sub-circuit acts as an intermediary between the input and output sub-circuits, using clock signals to mediate signal transmission timing. This intermediary control mechanism ensures signal accuracy without requiring complex direct coupling between input and output stages, simplifying the overall circuit structure.
4Adaptability or versatility
If cascaded shift registers are used to control multiple rows, then display coverage increases, but circuit complexity increases
Solution Approach 1:
Multiple shift register stages are nested in a cascaded configuration where the output of one stage feeds into the input of the next. This nesting allows a single modular circuit design to be expanded to control multiple rows of pixel circuits, increasing display coverage while maintaining consistent circuit complexity per stage rather than proportionally increasing overall complexity.
Data Source
AI summary
A shift register includes an input sub-circuit, a control sub-circuit, an output sub-circuit and a reset sub-circuit. The input sub-circuit is configured to transmit an input signal from an input signal terminal to a pull-up node. The control sub-circuit is configured to transmit a clock signal from a clock signal terminal to the control node. The output sub-circuit is configured to transmit a second voltage signal from a second voltage signal terminal to a first output signal terminal, and to transmit a first voltage signal from a first voltage signal terminal to the first output signal terminal. The reset sub-circuit is configured to transmit the second voltage signal to the control node to reset the control node, and to transmit a third voltage signal from the third voltage signal terminal to the pull-up node to reset the pull-up node.