Shift Register Sub-Circuits for Gate Driving Signal Conversion
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Solution Overview
Problem
The integration of gate driving circuits directly onto display panel arrays, as seen in the GOA technique, faces challenges in efficiently converting clock signals into on/off signals for gate lines due to limitations in existing shift register designs, which affects the resolution and bezel size of display panels.
Innovation Solution
A shift register design with multiple terminals and sub-circuits, including input, level control, output, and reset sub-circuits, that receives and processes various signals to output gate driving signals, reducing noise and enabling both forward and reverse scan modes, thereby improving the applicability and reducing the number of shift registers needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional shift register design is used, then the circuit structure is simple, but the signal conversion efficiency is low and noise reduction is insufficient
Solution Approach 1:
The shift register is divided into multiple functional sub-circuits: input sub-circuit, level control sub-circuit, output sub-circuit, and reset sub-circuit. Each sub-circuit performs a specific function in the signal processing chain, improving signal conversion efficiency while maintaining manageable complexity through functional decomposition
Solution Approach 2:
The shift register circuit is designed to output two gate driving signals simultaneously through different output terminals, enabling it to drive multiple gate lines with a single circuit instance. This multi-functionality improves signal conversion efficiency by reducing the total number of shift registers needed
2Productivity
If multiple shift registers are used to drive gate lines, then the signal output capability is sufficient, but the circuit footprint increases
Solution Approach 1:
A single shift register circuit is designed with multiple output terminals that can simultaneously drive different gate lines. The circuit responds to clock signals at different terminals to generate multiple output signals, effectively replacing multiple shift register circuits and reducing the overall circuit footprint
Solution Approach 2:
Multiple functional components (input circuit, level control circuit, output circuit, reset circuit) are merged into a single integrated shift register unit. This consolidation maintains the signal output capability while reducing the total circuit area by eliminating redundant structures
3Adaptability or versatility
If the shift register outputs multiple gate driving signals, then the applicability improves, but the device complexity increases
Solution Approach 1:
The shift register is designed with multiple clock terminals and output terminals, enabling it to respond to different input signals and generate different output signals simultaneously. This multi-functional design improves applicability by allowing the same circuit to drive multiple gate lines with different scanning directions and timing requirements
Solution Approach 2:
The device is segmented into distinct functional sub-circuits, each handling specific tasks. This segmentation makes the complex multi-functional device easier to design, analyze, and manufacture by breaking down the overall complexity into manageable functional modules
Data Source
AI summary
A shift register includes a first input sub-circuit configured to transfer a first input signal at a first input terminal to a first node in response to a first scan signal at a first scan terminal being active, a first level control sub-circuit configured to transfer a first power supply voltage at a first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential, and an output sub-circuit configured to transfer a first clock signal at a first clock terminal to a first output in response to the first output control node being at an active potential, and to transfer a second clock signal at a second clock terminal to a second output terminal in response to the second output control node being at an active potential.