Shift Register Sub-Stage Segmentation for OLED Scan Pulse Stability
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Solution Overview
Problem
Conventional shift registers in organic light emitting diode (OLED) display devices face challenges in stably outputting scan pulses of composite waveforms due to deviations in driving currents, requiring larger transistors which increase device size.
Innovation Solution
A shift register design that includes multiple stages generating A-scan and B-scan pulses using A-clock, B1-clock, and B2-clock pulses, allowing for stable output without the need for large transistors by bootstrapping voltages and optimizing pulse widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multiplexer structure is used to output scan pulses of composite waveform, then the scan pulse can be generated by switching fixed voltage, but the output transistor size must be increased resulting in increased display device size
Solution Approach 1:
The scan pulse output is segmented into two separate waveforms (A-scan pulse and B-scan pulse) with different widths and timings. Each waveform is generated by dedicated sub-stages (A-sub-stage and B-sub-stage) rather than using a single multiplexer structure, eliminating the need for large output transistors while maintaining stable output.
Solution Approach 2:
The patent introduces a temporal dimension by generating A-scan and B-scan pulses at different timings with different widths. This dimensional separation in time domain allows the use of smaller transistors that would be insufficient for switching fixed voltage in a conventional multiplexer approach.
2Reliability
If transistor size is increased to prevent voltage attenuation, then stable scan pulse output is achieved, but the display device area increases
Solution Approach 1:
The patent changes the operating parameters by generating scan pulses with different widths and timings (A-scan and B-scan) rather than using a single fixed voltage waveform. This parameter differentiation allows each pulse type to be optimized for its specific requirements, enabling stable output with smaller transistors.
Solution Approach 2:
The patent employs dynamic control where the A-sub-stage and B-sub-stage independently control voltages at respective set and reset nodes based on clock signals. This dynamic voltage control adapts to the specific timing and width requirements of each scan pulse type, maintaining voltage stability without requiring oversized transistors.
Data Source
AI summary
A shift register includes a plurality of stages for sequentially outputting A-scan pulses and B-scan pulses. At least one of the stages includes an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the A-reset node and any one A-clock pulse, a B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse based on the voltage at the B-set node, the voltage at the B-reset node and any one B1-clock pulse, and a scan output controller for generating a corresponding one of the A-scan pulses and a corresponding one of the B-scan pulses.