Shift Register Start Pulse Surge Protection
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Solution Overview
Problem
The reduction in pitch of gate signal lines in high-resolution display panels increases the risk of electrostatic discharge (ESD) surges in the start pulse wire, potentially damaging the thin film transistors (TFTs) due to the reduced dimension of unit register circuits in the shift register of gate signal line driving circuits.
Innovation Solution
The design includes a gate signal line driving circuit with a shift register that uses two circuit units at the end of the cascade to receive a start pulse in parallel, increasing the capacity of the gate electrodes connected to the start signal line, thereby reducing the surge voltage and protecting the TFTs. This configuration involves a first circuit unit that refrains from outputting a gate signal and a second unit that outputs a gate signal, with each unit having distinct functions to manage the pulse transfer and generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pitch of gate signal lines is reduced to increase display resolution, then the display resolution is improved, but the electrostatic discharge surge risk increases and may damage TFTs
Solution Approach 1:
The patent divides the single start pulse reception point into multiple reception points by connecting two circuit units (first and second circuit units) in parallel to the start pulse wire. This segmentation distributes the ESD surge across multiple TFT gate electrodes, preventing concentration of harmful voltage at a single point and protecting the circuit from damage while maintaining high display resolution.
2Measurement precision
If the dimension of unit register circuits is reduced to accommodate higher resolution, then the display resolution is improved, but the surge tolerance decreases and TFT damage risk increases
Solution Approach 1:
The patent segments the start pulse reception function across two circuit units connected in parallel. By distributing the surge reception across multiple gate electrodes of different TFTs, the system achieves both reduced circuit dimensions for high resolution and improved surge tolerance through the distributed architecture.
Solution Approach 2:
The patent implements beforehand cushioning by designing the circuit with redundant TFTs (first and second circuit units) that are prepared in advance to handle ESD surges. When a surge occurs, the parallel configuration provides alternative current paths and distributes the voltage stress, cushioning the impact on any single TFT and ensuring continued reliable operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the surge tolerance of the shift register, reducing the adverse effects of ESD and ensuring the reliability of the gate signal line driving circuit, even with reduced dimensions, by distributing the start pulse voltage across multiple TFTs.
Implementation Method 1
an electrostatic discharge (ESD) surge can occur in the start pulse wire
Data Source
AI summary
To improve surge tolerance of a shift register constituting a gate signal line driving circuit formed on a substrate of a flat panel display. A gate signal line driving circuit includes a shift register composed of a plurality of cascaded unit register circuits, and sequentially outputs gate signals to a plurality of gate signal lines. Of the unit register circuits, two register circuits positioned on the leading end side for the shift operation of the shift register receive a start signal in parallel to operate. The two register circuits respectively output signals to mutually different destinations such that an output signal from one of the two register circuits is inputted via a gate signal generation circuit to a gate signal line, while an output signal from the other register circuit is inputted into its downstream unit register circuit.