Shift Register Reset Circuit for Gate Pulse Tail Suppression
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Solution Overview
Problem
Manufacturing process variations in transistors within the pull-down circuit of shift registers can cause premature leakage of control signals, leading to abnormal image display due to incomplete turning off of gate driving pulses, resulting in a tail phenomenon that wrongly charges pixels.
Innovation Solution
A resetting circuit is introduced, comprising a reset driving module and a reset module, which regulates the voltage on the output terminal of the shift register by using enable signals and reset control signals to ensure proper switching to a gate-off voltage level, preventing premature voltage leakage and tail phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the pull-down circuit uses transistors with standard manufacturing tolerance, then the manufacturing cost is reduced and ease of manufacture is improved, but manufacturing process variations cause premature leakage of control signals leading to tail phenomenon and abnormal image display
Solution Approach 1:
An intermediate resetting circuit is introduced between the shift register output and the pixel charging circuit. This resetting circuit includes a resetting transistor whose gate is controlled by a resetting signal, and whose source/drain forms an electrical path between the shift register output terminal and the gate-off voltage level. This intermediary component ensures that even with transistor parameter variations in the pull-down circuit, the gate driving pulse can be reliably reset to the gate-off level, preventing premature leakage and tail phenomenon while maintaining standard manufacturing tolerances.
2Manufacturing precision
If the pull-down circuit transistors have large manufacturing variations, then manufacturing precision requirements are relaxed, but the control signal leaks prematurely causing the gate driving pulse to not turn off properly
Solution Approach 1:
The resetting circuit operates based on a resetting signal that is generated in response to the operation state of the shift register. When the shift register completes its gate driving pulse output, the resetting signal is activated to turn on the resetting transistor, which then actively pulls the output terminal voltage back to the gate-off level. This feedback mechanism ensures that regardless of transistor parameter variations in the pull-down circuit, the output is reliably reset, preventing tail phenomenon and ensuring proper pixel charging.
3Ease of operation
If the control signal Q(n) is allowed to leak to Vss during the time duration t, then the reset timing is simplified, but the gate driving pulse G(n) occurs tail phenomenon and pixels are wrongly charged
Solution Approach 1:
The resetting circuit applies preliminary anti-action by preparing the resetting transistor to activate before the control signal Q(n) can cause premature leakage. The resetting transistor is designed to turn on in response to the resetting signal at the appropriate timing, creating a counteracting electrical path that prevents the control signal from leaking to Vss during the critical time duration. This preliminary protective action eliminates the tail phenomenon and prevents wrong pixel charging while maintaining simplified reset timing control.
Data Source
AI summary
An exemplary resetting circuit adapted for regulating a voltage on an output terminal of a shift register is disclosed. The resetting circuit includes a reset driving module and a reset module. The reset driving module is received with an enable signal to output a control voltage signal to an output terminal of the reset driving module. The reset module is electrically coupled to the output terminal of the shift register and the output terminal of the reset circuit driving module, and is controlled by the control voltage signal on the output terminal of the reset driving module to determine whether switching on an electrical path between the output terminal of the shift register and a gate-off voltage level.