Shift Register Tailing Reduction via Node Potential Control
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Solution Overview
Problem
The tailing phenomenon occurs in shift registers due to the unsaturated state of PMOS transistors, resulting in insufficient voltage at the output terminal, which affects the display effect in display panels.
Innovation Solution
A display panel with a driver circuit featuring an N-stage cascaded shift register, including a first, second, third, and fourth control unit, where the fourth control unit controls the potential of a third node to be a low level signal for a specific time period, ensuring the transistor approaches saturation state and preventing tailing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the PMOS transistor operates in an unsaturated state during signal transition, then the transistor can switch quickly, but the output voltage cannot reach the target voltage level, causing tailing phenomenon
Solution Approach 1:
The patent applies preliminary action by pre-charging the third node to a high voltage level before the signal transition occurs. This preparatory voltage establishment ensures that when the PMOS transistor switches, the output can rapidly reach the target voltage level without tailing, while still maintaining quick switching performance through the unsaturated operation mode.
2Speed
If the gate and source potentials of the PMOS transistor are both at Vgl during transition, then the transistor operates in unsaturated state for fast switching, but the drain output voltage only reaches |Vgl|−|Vth| instead of the target Vgl
Solution Approach 1:
The patent introduces an intermediary mechanism through the third node and associated circuitry that mediates between the unsaturated switching operation and the required output voltage accuracy. This intermediary structure allows the transistor to operate in the unsaturated state for fast switching while the third node provides the necessary voltage boosting to achieve the accurate target output level.
Data Source
AI summary
Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded, wherein N is a number greater than or equal to 2; where the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control unit comprising a first capacitor, a first transistor and a second transistor, where a second plate of the first capacitor is connected to a drain of the first transistor, a source of the second transistor is connected to a first node, and a drain of the second transistor is connected to the third node.