Shift Register Testing Circuit for IC Core Coverage
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Solution Overview
Problem
The existing testing methodologies for semiconductor integrated circuits, particularly in System on Chip (SoC) circuits with multiple functional cores, face challenges in reusing design and test methodologies without re-engineering, leading to limitations in achieving full test coverage and flexibility in controlling the testing process.
Innovation Solution
A testing circuit and method that incorporates a shift register circuit with a multiplexer for routing serial and parallel inputs, enabling dynamic control through additional update mechanisms triggered by data in the shift register, and a Wrapper Instruction Register architecture that supports both standard and continuous update modes for enhanced test flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a standard Wrapper Instruction Register architecture is used, then the testing process is simplified and standardized, but test flexibility and coverage for embedded cores are limited
Solution Approach 1:
The patent implements dynamic update mechanisms that allow the Wrapper Instruction Register to operate in multiple modes: standard update mode for simplicity and continuous update mode for enhanced flexibility. This dynamic capability enables the system to adapt its operation based on testing requirements, resolving the contradiction between ease of operation and test flexibility.
Solution Approach 2:
The enhanced Wrapper Instruction Register architecture provides multi-functionality by supporting both standard and continuous update modes, enabling it to handle diverse testing scenarios including embedded cores and hierarchical structures. This universal design allows a single register architecture to serve multiple testing purposes.
2Reliability
If multiple test runs are conducted to achieve full coverage of embedded cores, then test coverage is improved, but testing time and productivity are reduced
Solution Approach 1:
The continuous update mode enables uninterrupted testing operations where the Wrapper Instruction Register can be updated without stopping the test sequence. This continuity allows full coverage of embedded cores to be achieved in a single test run rather than requiring multiple sequential test runs, thereby improving productivity while maintaining comprehensive test coverage.
3Adaptability or versatility
If additional update mechanisms are added to the Wrapper Instruction Register, then test flexibility is enhanced, but device complexity increases
Solution Approach 1:
The patent introduces dynamic update mechanisms that add flexibility to the Wrapper Instruction Register architecture. These mechanisms include additional control logic and data paths that enable continuous update mode, allowing the register to adapt its operation based on testing requirements while maintaining a manageable level of complexity through systematic design.
4Productivity
If design reuse is implemented without re-engineering test methodology, then design productivity is improved, but test coverage and reliability may be compromised
Solution Approach 1:
The enhanced Wrapper Instruction Register architecture provides a universal testing platform that can handle both standard and embedded core testing through its multiple update modes. This allows design reuse without re-engineering test methodology while maintaining comprehensive test coverage, as the same register architecture adapts to different testing scenarios through its flexible update mechanisms.
Data Source
AI summary
A testing circuit has a shift register circuit (76) for storing instruction data for the testing of an integrated circuit core. Each stage of the shift register circuit comprises a first shift register storage element (32) for storing a signal received from a serial input (wsi) and providing it to a serial output (wso) in a scan chain mode of operation, and a second parallel register storage element (38) for storing a signal from the first shift register storage element and providing it to a parallel output in an update mode of operation. The testing circuit further comprises a multiplexer (70) for routing either a serial test input to the serial input (wsi) of the shift register circuit or an additional input (wpi[n]) into the serial input of the shift register circuit (76). In a preferred example, the testing circuit further comprises a control circuit (78) which responds to a specific value of data stored in at least one stage of the shift register to generate an update signal for setting the other shift register stages into the update mode of operation.