Shift Register Timing Control for Gate Driving Circuit Power Reduction

The patent implements dynamic output timing control where the gate driving circuit can switch between normal output timing and exceptional output timing based on display content requirements. The selection sub-circuit dynamically selects which output sub-circuit to activate, allowing the system to adapt its timing behavior to minimize power consumption while maintaining compatibility with conventional circuits when exceptional timing is not needed.

The patent changes the timing parameter of the output signals by providing two different output timing modes (normal and exceptional). The exceptional output timing sub-circuit generates inverted timing sequences that reduce the frequency of polarity inversions in the liquid crystal display, thereby reducing power consumption without requiring a complete redesign of the gate driving circuit architecture.

The selection sub-circuit acts as an intermediary that intelligently chooses between normal and exceptional output timing modes based on the specific display content requirements. This mediator ensures that abnormal timing is only applied when necessary, maintaining output stability and compatibility with conventional display refresh operations while still achieving power consumption reduction when beneficial.

The system dynamically switches between normal and exceptional timing modes rather than using a fixed timing scheme. This dynamic adaptation allows the circuit to maintain reliable operation during standard display refresh cycles while occasionally employing exceptional timing to reduce power consumption during specific display content conditions, thus balancing reliability and energy efficiency.