Shift Register Circuit Timing Control for Amorphous Silicon Stability
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Solution Overview
Problem
Scanning drivers using amorphous silicon transistors in image display and read apparatuses face challenges with low operating frequencies and deteriorating element characteristics, making it difficult to maintain effective display or read driving over time, especially in high-resolution or large-screen applications.
Innovation Solution
A shift register circuit with cascade-connected signal holding circuits, including input, output, and reset control circuits, utilizing control clock signals to manage signal timing and phase, which allows for efficient output signal generation and suppression of characteristic deterioration, even with low electron mobility switching elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon transistors are used in scanning drivers, then manufacturing simplicity and integration are improved, but operating frequency and element characteristic stability deteriorate
Solution Approach 1:
The patent applies preliminary action by setting the output signal termination timing before the reset signal application start timing. This preemptive timing arrangement ensures that the output signal is fully terminated before the reset operation begins, preventing any potential interference or instability that could arise from overlapping operations. This preliminary timing configuration compensates for the lower electron mobility of amorphous silicon transistors by ensuring clean signal transitions without requiring higher operating frequencies.
2Adaptability or versatility
If amorphous silicon transistors are used in scanning drivers, then integration with display panels is improved, but operating frequency deteriorates
Solution Approach 1:
The patent applies dynamics by implementing a flexible timing control mechanism where the output signal termination timing is dynamically set relative to the reset signal application timing. This dynamic timing arrangement allows the circuit to adapt its operation to the specific characteristics of amorphous silicon transistors, optimizing performance within the constraints of lower electron mobility while maintaining seamless integration with display panels.
3Device complexity
If conventional shift register circuits are used, then circuit simplicity is improved, but signal timing control and characteristic deterioration suppression deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the shift register circuit into distinct functional blocks: input control circuits, output control circuits, and reset control circuits. Each block is independently controlled with specific timing parameters. This segmentation allows precise timing control of signal termination before reset signal application, thereby suppressing characteristic deterioration while maintaining reasonable circuit simplicity through modular design.
Data Source
AI summary
A shift register circuit includes a plurality of cascade-connected signal holding circuits each of the signal holding circuits includes an input control circuit to which an input signal is applied, and which fetches and holds the input signal, an output control circuit to which a first control clock signal is applied, and which outputs an output signal corresponding to timings of the held input signal and the first control clock signal, and a reset control circuit to which a reset signal is applied, and which initializes a signal level of the input signal held in the input control circuit. A timing at which the output signal is terminated is set to be ahead of an application start timing of the reset signal.