Shift Register Transistor Reduction for Display Stability
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Solution Overview
Problem
The existing shift registers in display apparatuses require a large number of transistors to prevent flow-through currents during all-on operations, which increases the complexity and reduces the signal level of output signals due to the on resistance and threshold voltage of NMOS transistors.
Innovation Solution
A shift register design that reduces the number of transistors by using a first output transistor connected between the output terminal and a clock terminal, a second output transistor connected between the output terminal and a predetermined potential node, and control devices to manage the signal levels and clock signals for efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS transistors are used to prevent flow-through currents during all-on operations, then the shift register operation becomes stable, but the number of transistors increases and the signal level decreases due to on resistance and threshold voltage
Solution Approach 1:
The invention extracts and eliminates the unnecessary NMOS transistors (Q6 and Q8) that were previously required for flow-through current prevention. By reconfiguring the circuit to use only PMS transistors (Q5 and Q7) for this function, the patent removes the problematic NMOS components that caused signal level degradation and increased device complexity, while maintaining operational stability through the modified PMS-only architecture
Solution Approach 2:
The invention merges the functions of multiple transistors into a simplified PMS-based configuration. By combining the flow-through current prevention function with the existing PMS transistor structure, the patent eliminates the need for separate NMOS transistors, thereby reducing the total transistor count and simplifying the device while maintaining all necessary functions
2Adaptability or versatility
If NMOS transistors are added to prevent flow-through currents, then the shift register can perform all-on operations, but the on resistance and threshold voltage reduce the output signal level
Solution Approach 1:
The invention extracts and removes the NMOS transistors (Q6 and Q8) that were degrading the output signal level through their on resistance and threshold voltage. By eliminating these components and relying solely on PMS transistors, the patent restores the output signal level while preserving the all-on operation capability through the reconfigured circuit architecture
3Reliability
If more transistors are used to ensure stable operation during power supply transitions, then the shift register becomes more reliable, but the layout area increases
Solution Approach 1:
The invention extracts and eliminates the redundant NMOS transistors that were increasing the layout area. By removing Q6 and Q8 and simplifying the circuit to use only necessary PMS transistors, the patent reduces the overall layout area while maintaining operation stability during power supply transitions through the optimized transistor configuration
Solution Approach 2:
The invention makes the PMS transistors perform multiple functions - they handle both the flow-through current prevention and the output signal generation. This multi-functionality eliminates the need for separate NMOS transistors, thereby reducing layout area while maintaining reliability during power supply transitions
Data Source
AI summary
A shift register according to the present invention is a shift register in which a plurality of unit circuits are connected in cascade, wherein the unit circuit includes a first output transistor whose current path is connected between an output terminal and a clock terminal to which a first clock signal is provided; a second output transistor whose current path is connected between the output terminal and a predetermined potential node; a setting device which, when a control signal is active, sets a signal level of the output terminal to a predetermined signal level; a first output control device which provides a signal level of the control signal to a control electrode of the first output transistor to turn off the first output transistor when the control signal is active; and a second output control device which turns off the second output transistor when the control signal is active.