Shift Register Transistor Reduction for Narrow Frame Displays
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Solution Overview
Problem
Conventional gate driver-on-array (GOA) circuits for display panels require a significant number of transistors to maintain normal operation, which limits the reduction of frame width due to the inclusion of pulling-up and pulling-down nodes, making it difficult to achieve a super-narrow or frameless design.
Innovation Solution
A shift register design that reduces the number of transistors by removing the pulling-down node, utilizing a first input module, output module, reset module, and second input module connected to clock signals and a low-level voltage line, allowing for efficient potential control and noise voltage discharge, thereby reducing the frame width occupied by the GOA circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a circuit structure with pulling-up node and pulling-down node is used to maintain normal operation, then the reliability of the GOA circuit is improved, but the number of transistors increases to approximately ten per unit, which increases the frame width
Solution Approach 1:
The patent extracts and removes the pulling-down node from the traditional circuit structure, keeping only the pulling-up node. This extraction eliminates the transistors dedicated to pulling-down operations while maintaining the essential functionality of the GOA circuit through alternative discharge paths and clock signal control mechanisms.
Solution Approach 2:
The patent merges the functions of multiple transistors into a reduced set of transistors. By combining the pulling-up function with optimized discharge mechanisms and utilizing clock signals for potential control, the circuit achieves normal operation with fewer transistors, thereby reducing the frame width.
2Reliability
If multiple transistors are disposed to adjust potentials of pulling-up node and pulling-down node, then the reliability of the circuit is improved, but the device complexity increases
Solution Approach 1:
The patent extracts and eliminates the pulling-down node and its associated transistors from the circuit structure. This removal simplifies the device by reducing the transistor count while maintaining reliability through alternative potential control methods using clock signals and the remaining pulling-up transistors.
Solution Approach 2:
The patent makes the remaining transistors multi-functional by designing them to handle both pulling-up operations and potential discharge functions. The clock signals are utilized to control these transistors for multiple purposes including potential adjustment and noise discharge, thereby reducing the need for dedicated transistors for each function.
3Ease of operation
If the GOA circuit is disposed at two sides of active display area with black matrix area, then the normal function is achieved, but the frame width cannot be reduced further
Solution Approach 1:
The patent extracts and removes the black matrix area requirement by eliminating the pulling-down node that necessitated its presence for shading. This allows the GOA circuit to be positioned closer to the active display area, enabling super-narrow or frameless designs while maintaining normal display function.
Solution Approach 2:
The patent changes the spatial arrangement by reducing the vertical or horizontal space required for the GOA circuit through transistor reduction. This dimensional optimization allows the circuit to fit within narrower frames without compromising functionality, enabling new design possibilities for display panels.
Data Source
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AI summary
A shift register and a driving method therefor, a gate drive circuit and a display apparatus. The shift register comprises: a first input module (11) for pulling up the potential of a first node under the effect of a signal received by an input end, an output module (13) for pulling up the electric potential of an output end under the effect of the electric potential of the first node, a reset module (15) for pulling down the electric potential of the first node under the effect of a signal received by a reset end, and an output pull-down module (14) for pulling down the electric potential of the output end under the effect of a first clock signal, wherein the first input module (11), the output module (13), the output pull-down module (14) and the reset module (15) are all connected to the first node; and the shift register also comprises a second input module (12) for connecting the input end to the first node under the effect of the first clock signal within working hours of the first input module (11) and the output pull-down module (14). A pull-down node is removed from the shift register, so that the number of transistors can be reduced, which is beneficial for reducing the frame width occupied by a gate drive circuit.