Shift Register Using Unified Clock Signals for Display Devices
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Solution Overview
Problem
Conventional display devices require two separate shift registers and clock signal circuits due to different pulse widths for scanning and data writing signals, leading to a wide frame area.
Innovation Solution
A shift register design that includes multiple input and shifting modules, utilizing a set of clock signals with the same period and duty cycle to output both scanning and data writing signals, reducing the need for additional clock signal sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two different shift registers are used to output scanning voltage signal and data input signal, then the different pulse widths of the two signals can be satisfied, but the frame area of the display device becomes too wide
Solution Approach 1:
The patent combines two separate shift registers into a single shift register that can output both scanning voltage signals and data input signals. This is achieved by using one set of clock signals to control a unified shift register structure that generates both signal types, thereby reducing the frame area while maintaining the ability to satisfy different pulse width requirements through appropriate clock signal configuration
Solution Approach 2:
The shift register is designed with multi-functionality to output both scanning voltage signals and data input signals using a single set of clock signals. The shift register can selectively generate different signal types based on control inputs, making it a universal signal generation unit that eliminates the need for separate dedicated shift registers for each signal type
2Manufacturing precision
If two sets of clock signals are used to drive two different shift registers, then the different pulse widths of the two signals can be achieved, but the complexity of the clock signal circuit increases
Solution Approach 1:
The patent merges two separate clock signal circuits into a single clock signal circuit that generates both sets of clock signals (first clock signal and second clock signal) using the same structural framework. This unified clock signal circuit reduces overall circuit complexity while still providing the necessary different pulse widths for different signal types through differentiated clock signal parameters
Solution Approach 2:
The clock signal circuit is designed with multi-functionality to generate both first clock signals and second clock signals that have different characteristics (different pulse widths). This universal clock signal generation capability allows a single circuit to fulfill the roles of what would traditionally require separate dedicated clock signal circuits
Data Source
AI summary
The present invention provides a shift register, in which first and second shifting modules are turned on by the first input module according to a first clock signal; the first shifting module shiftingly outputs a first input signal when it is on; a first reset module turns off the first shifting module according to a third clock signal and outputs the first input signal; the second shifting module shiftingly outputs a second input signal when it is on; a second input module outputs a turning-on signal or a turning-off signal to a second reset module according to the first clock signal; a second reset module outputs the second input signal when it is turned on; and a third input module turns off the second shifting module according to the second clock signal. The first, second and third clock signals have a same clock period and a same duty cycle.