Shift Register Unit With Adjustable Duty Cycle For OLED Displays

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Solution Overview

Problem

Existing shift register circuits in OLED display panels face challenges in maintaining accurate control over the threshold voltage of drive transistors, which affects the electric current and light emission time, requiring additional circuits for compensation and timing control.

Innovation Solution

A shift register unit with a simple circuit structure incorporating input, control, hold, and output circuits, utilizing transistors and capacitors to manage voltages and clock signals, allowing for an adjustable duty cycle output signal, reducing the layout area and enabling high-resolution displays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a conventional shift register circuit is used to control gate scanning and light emission, then the control function is achieved, but the circuit structure becomes complex and occupies large layout area

Engineering Contradiction:
Improvecircuit structureVSAvoidlayout area
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The patent combines multiple control functions (gate scanning signal output and light emission timing control) into a single integrated shift register unit. This unit simultaneously generates the gate scanning signal and controls the light emission time sequence, eliminating the need for separate circuits and reducing overall complexity and layout area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shift register unit is designed to perform multiple functions: it acts as both a gate scanning signal generator and a light emission controller. By making the circuit universal, the patent reduces the total number of components needed while maintaining all necessary control capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If additional shift register circuits are added to control light emission timing, then the light emission control is improved, but the device complexity increases

Engineering Contradiction:
Improvelight emission controlVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the light emission control function with the existing shift register circuit by adding a light emission control signal output terminal and associated control logic to the same unit that generates gate scanning signals. This integration maintains reliable control while avoiding the complexity of completely separate circuits.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If more transistors and circuits are used for threshold voltage compensation and timing control, then the control precision is improved, but the layout area increases

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidlayout area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The shift register unit is designed to handle multiple control tasks (gate scanning, light emission timing, and threshold voltage compensation control) within a single integrated structure. This multi-functional design reduces the total transistor count and layout area while maintaining the necessary control precision through careful circuit design.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10629108B2Shift register unit and drive method thereof, shift register and display device
Publication Date: 2020.04.21 BOE TECHNOLOGY GROUP CO LTD
  • US10629108B2 patent drawing
  • US10629108B2 patent drawing
  • US10629108B2 patent drawing

AI summary

Embodiments of the present disclosure provide a shift register unit, which includes an input circuit configured to control a voltage of a first node based on an input signal and a first clock signal; an first control circuit configured to control a voltage of a second node based on a first voltage, the first clock signal, and the voltage of the first node; an second control circuit configured to control a voltage of a third node based on the voltage of the second node and a second clock signal; a first hold circuit configured to hold the voltage of the first node based on a second voltage and the voltage of the third node; a second hold circuit configured to hold the voltage of the second node and of the third node; and an output circuit configured to output the first voltage or the second voltage from an output terminal.