Shift Register Unit for AMOLED Gate Driving
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Solution Overview
Problem
Existing AMOLED display technologies face challenges in efficiently controlling sub-pixels for independent and continuous light emission, particularly in managing threshold voltage compensation and data signal writing times, which can lead to display defects and reduced refresh rates.
Innovation Solution
A shift register unit and driving method are introduced, providing multiple gate driving signals through a circuit structure with transistors of different semiconductor types, allowing for separate control of threshold voltage compensation and data signal writing times, thereby improving pixel circuit performance and reducing display defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional shift register unit is used for gate driving in AMOLED displays, then the circuit structure is simple, but the threshold voltage compensation and data signal writing cannot be separately controlled, leading to display defects and reduced refresh rates
Solution Approach 1:
The shift register unit is segmented into multiple independent control paths: a first control circuit for threshold voltage compensation and a second control circuit for data signal writing. This segmentation allows separate control of compensation time and writing time, enabling independent optimization of each function to improve display quality and refresh rate without excessive complexity increase.
Solution Approach 2:
The patent implements dynamic control of signal timing by using different clock signals (first clock signal line CK1, second clock signal line CB1) and control nodes (P1, P2) that can independently adjust the duration and timing of compensation and writing operations. This dynamic control allows the circuit to adapt timing parameters to achieve full threshold voltage compensation and rapid data writing.
2Reliability
If threshold voltage compensation time is extended to ensure full compensation, then display defects are reduced, but the overall refresh rate decreases
Solution Approach 1:
The threshold voltage compensation is performed as a preliminary action before data signal writing through the first control circuit. By completing the compensation phase in advance with dedicated timing control, the circuit ensures full threshold voltage compensation is achieved without encroaching on the data writing time, thereby maintaining high refresh rates while ensuring compensation completeness.
Solution Approach 2:
The timing cycle is segmented into distinct compensation phase and writing phase. The first control circuit handles compensation during its designated time window controlled by clock signal CK1, while the second control circuit handles data writing during its time window controlled by clock signal CB1. This temporal segmentation allows both operations to be fully completed within each refresh cycle without conflict.
3Productivity
If data signal writing is performed rapidly to improve refresh rate, then productivity increases, but threshold voltage compensation may be insufficient, leading to display defects
Solution Approach 1:
Threshold voltage compensation is executed as a preliminary action before rapid data signal writing. The first control circuit completes the compensation process during the first clock cycle phase, ensuring full compensation is achieved before the second control circuit begins the rapid data writing operation in the subsequent phase, thus preventing display defects while maintaining high refresh rates.
Solution Approach 2:
The circuit uses dynamic timing control with separate clock signals to coordinate the compensation and writing operations. The first control circuit operates during the period when control node P1 is activated, while the second control circuit operates when control node P2 is activated. This dynamic coordination ensures compensation is fully completed before rapid writing begins, maintaining both reliability and productivity.
Data Source
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AI summary
A shift register unit includes an input circuit, a first control circuit, a second control circuit, and an output circuit. The input circuit is configured to provide a signal of a first clock signal line or a first power line to a first control node under the control of a second clock signal line, a first input terminal, and a second control node. The first control circuit is configured to provide a signal of the first power line or a second power line to a first output terminal under the control of the first control node and the second control node. The second control circuit is configured to provide a signal of the first power line or the second power line to a second output terminal under the control of the first output terminal. The output circuit is configured to output an effective level signal of the first power line or the second power line to a third output terminal under the control of a control signal line and the second output terminal. Within the time of one frame, a duration of an effective level signal provided by the third output terminal is longer than that of an effective level signal provided by the second output terminal.