Shift Register Unit Circuit Simplification for Display Devices

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Solution Overview

Problem

Conventional shift register units for display devices have complex circuit structures and difficulty in providing a stable waveform, making it challenging to efficiently scan and drive pixel units as the number of pixels increases.

Innovation Solution

A simplified shift register unit design incorporating a control module, first and second output modules, and sub-modules such as control, resetting, pull-up, and bleeder sub-modules, utilizing P-type transistors and capacitors to control signal potentials and simplify the circuit structure, enabling stable voltage output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional shift register unit uses multiple transistors and capacitors to control signal potentials, then the circuit can perform signal control functions, but the circuit structure becomes complex and the waveform stability deteriorates

Engineering Contradiction:
Improvewaveform stabilityVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the shift register unit into distinct functional modules: a control module that generates control signals, a first output module that outputs control signals to pixel units, and a second output module that outputs clock signals. This segmentation allows each module to be optimized independently, simplifying the overall circuit structure while maintaining waveform stability through dedicated functional blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control module serves multiple functions: it generates both first control signals for the first output module and second control signals for the second output module, and also performs resetting functions. This multi-functionality reduces the total number of components needed while maintaining reliable signal control through centralized management.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If the number of pixels in a display device increases, then the display resolution improves, but the layout area of each shift register unit must be reduced

Engineering Contradiction:
Improvedisplay resolutionVSAvoidlayout area of shift register unit
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

By segmenting the shift register unit into compact functional modules (control module, first output module, second output module), the patent achieves a space-efficient layout that reduces the area occupied by each shift register unit, thereby supporting higher display resolutions with more pixels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple signal control functions into integrated modules. The control module generates multiple control signals, and the output modules handle both control and clock signals, merging functions that would traditionally require separate components. This consolidation reduces the overall layout area while maintaining full functionality.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10210840B2Shift register unit, its driving method, gate driver circuit and display device
Publication Date: 2019.02.19 BOE TECHNOLOGY GROUP CO LTD
  • US10210840B2 patent drawing
  • US10210840B2 patent drawing
  • US10210840B2 patent drawing

AI summary

The present disclosure provides a shift register unit, its driving method, a gate driver circuit and a display device. The shift register unit includes a control module, a first output module and a second output module. The first output module is connected to a first signal end, a first node and an output end. The second output module is connected to the output end, a second node and a first clock signal end. The control module is connected to the first node, the second node, the first signal end, a second signal end, a second clock signal end, a third clock signal end, an input signal end and a resetting signal end, and configured to control potentials at the first node and the second node.