Shift Register Unit DC Path Elimination in GOA Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The stability and power consumption of Gate Driver On Array (GOA) circuits in LCD display technology are compromised due to the formation of a DC path, which affects the charging efficiency and voltage stability of clock signals, leading to reduced performance and increased power consumption.
Innovation Solution
A shift register unit is designed with a first input sub-circuit, a first control sub-circuit, an output sub-circuit, and a second control sub-circuit, along with a noise reduction sub-circuit, to control the timing of input signals, clock signals, and voltage levels, preventing the formation of a DC path by ensuring that the potential of the first node does not compete with the potential of the second node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional GOA circuit is used, then the gate drive function is provided, but a DC path is formed causing increased power consumption and reduced stability
Solution Approach 1:
The circuit is divided into multiple sub-circuits (first input sub-circuit, first control sub-circuit, output sub-circuit, second control sub-circuit) that operate in distinct phases. Each sub-circuit handles specific timing functions to prevent simultaneous conduction paths, segmenting the current flow control to eliminate the DC path while maintaining gate drive functionality.
Solution Approach 2:
The circuit employs periodic clock signals (first clock signal and second clock signal) to control the timing of signal transmission through different sub-circuits. This periodic action ensures that signals are transmitted in alternating phases, preventing the formation of a continuous DC path while maintaining stable voltage levels across nodes.
2Productivity
If clock signals are transmitted through the circuit, then the gate drive operation is enabled, but charging efficiency is reduced due to voltage competition between nodes
Solution Approach 1:
The first control sub-circuit preliminarily processes the second input signal before it reaches the second control sub-circuit. This preliminary action prepares the signal in advance, ensuring proper voltage levels are established before the main clock signal transmission, thereby improving charging efficiency while maintaining voltage stability.
Solution Approach 2:
The first control sub-circuit acts as an intermediary between the input signals and the second control sub-circuit. It mediates the signal transmission by controlling when and how signals are passed along, preventing direct voltage competition between nodes while enabling efficient clock signal charging through controlled intermediate stages.
Data Source
AI summary
A shift register unit and a driving method thereof, a gate drive circuit, and a display device are disclosed. The shift register unit includes a first input sub-circuit, a first control sub-circuit, an output sub-circuit, and a second control sub-circuit. The first input sub-circuit is configured to output a first control signal of the first control signal terminal to the first control sub-circuit; the first control sub-circuit is configured to output a second input signal of the second input terminal to the first node, or the first control sub-circuit is configured to output the second input signal to the second control sub-circuit; the second control sub-circuit is configured to output a second clock signal to the second node; or the second control sub-circuit is configured to output a first voltage of the first voltage terminal to the second node under control of a level of the control node.