Shift Register Unit Reducing Output Delay and Attenuation
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Solution Overview
Problem
Existing shift registers suffer from long output delay and attenuation, leading to unstable operation and reduced driving margin, primarily due to prolonged transistor turn-on times and capacitor attenuation.
Innovation Solution
A shift register unit comprising twelve transistors and one capacitor, with specific connections among INPUT, RESET, CLK, CLKB, OUTPUT, and power supply terminals, designed to reduce reset delay and noise interference, enhancing stability and driving margin by optimizing transistor and capacitor interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional transistors and capacitors are used in the shift register, then the circuit structure is simple, but the output delay is long and attenuation occurs
Solution Approach 1:
The shift register circuit is segmented into multiple functional modules: input control module (M1-M3), clock control module (M5-M7), reset control module (M2, M4), and output module (M8-M12). Each module performs a specific function, allowing parallel operation and reducing overall delay while maintaining structural clarity
Solution Approach 2:
The circuit performs preliminary actions by pre-charging nodes and pre-positioning transistor states before the main signal transmission. The dual-clock system (CLK and CLKB) prepares the circuit state in advance, and the reset signal pre-configures the transistor gates, reducing the actual signal propagation delay
2Device complexity
If conventional transistors are used, then the device count is low, but the reset speed is slow and charging at nodes is affected
Solution Approach 1:
The reset function is segmented into dedicated reset transistors (M2, M4) that independently control different nodes. This segmentation allows simultaneous resetting of multiple nodes without interference, significantly improving reset speed compared to sequential resetting in conventional designs
Solution Approach 2:
The circuit employs periodic clock signals (CLK and CLKB) that alternately control the charging and discharging of nodes. This periodic action ensures that nodes are charged and reset in optimal sequences, maximizing reset speed while preventing charging conflicts
3Device complexity
If conventional shift register design is used, then the circuit is simple, but attenuation occurs and operating stability is poor
Solution Approach 1:
The circuit implements feedback mechanisms where the output state influences the control signals for subsequent operations. The dual-clock system provides feedback control, and the transistor gate connections create feedback loops that stabilize node voltages, preventing attenuation and ensuring reliable operation
Solution Approach 2:
The circuit changes operational parameters by using dual-clock signals with opposite phases (CLK and CLKB) to control different transistor groups. This parameter change allows the circuit to switch between charging and discharging states efficiently, maintaining stable operation and preventing signal attenuation across multiple stages
Data Source
AI summary
The disclosure discloses a shift register unit, a shift register, a display panel and a display, and belongs to display driving technology. The shift register unit comprises: twelve transistors M1, M2, . . . , M12; one capacitor C1; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one or more power supply terminals. The disclosure may decrease the output delay and attenuation, and improve an anti-interference capability, so that the shift register may operate stably and a driving margin of the shift register could be increased.