Shift Register Unit for Large-Area TFT-LCD Gate Driving

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Solution Overview

Problem

Conventional gate driving circuits in large-area TFT-LCDs suffer from waveform distortion in output signals due to cascaded shift register units, leading to poor performance and increased power consumption.

Innovation Solution

A shift register unit comprising an input circuit, output circuit, resetting and de-noising circuit, and pull-down node control circuit, which includes transistors and capacitors to manage voltage levels and control signals, ensuring proper coupling and decoupling of voltage terminals to minimize distortion and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional cascaded shift register units are used in large-area display panels, then the gate driving circuit can be formed on the display panel, but waveform distortion occurs in the output signal

Engineering Contradiction:
Improveoutput signal qualityVSAvoidcascaded shift register structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shift register unit is divided into multiple independent functional circuits: input circuit, output circuit, resetting circuit, and de-noising circuit. Each circuit handles specific signal processing tasks independently, preventing the accumulation of waveform distortion that occurs in conventional cascaded structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A pull-down node control circuit is introduced as an intermediary component to actively manage the potential at the pull-down node. This intermediary circuit compensates for waveform distortion by controlling the coupling between voltage terminals, ensuring signal integrity without increasing overall system complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If conventional shift register units are used, then the gate driving circuit can operate, but power consumption increases

Engineering Contradiction:
Improvegate driving operationVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The resetting circuit operates periodically to restore the pull-up node to its initial state, and the de-noising circuit periodically removes noise from the output signal terminal. This periodic operation reduces continuous power consumption while maintaining gate driving functionality.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The resetting circuit discards accumulated charge at the pull-up node when needed and recovers it when not needed, reducing unnecessary power consumption. The de-noising circuit similarly discards noise signals while preserving valid signal components, improving energy efficiency.

Inventive Principle:
Principle #34Discarding and recovering

3Reliability

If the pull-up node is continuously de-noised, then output signal quality improves, but power consumption increases

Engineering Contradiction:
Improveoutput signal qualityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The de-noising circuit is designed to automatically activate only when noise is present at the output signal terminal, using feedback from the output signal itself to control its operation. This self-service mechanism eliminates the need for continuous external control signals, reducing power consumption while maintaining signal quality.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11282469B2Shift register unit and method for driving the same, gate driving circuit and display apparatus
Publication Date: 2022.03.22 CHONGQING BOE OPTOELECTRONICS
  • US11282469B2 patent drawing
  • US11282469B2 patent drawing
  • US11282469B2 patent drawing

AI summary

The embodiments of the present disclosure disclose a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit configured to output an input signal from an input signal terminal to a pull-up node; an output circuit configured to output a clock signal from a clock signal terminal to an output signal terminal under control of a potential at the pull-up node; a resetting and de-noising circuit configured to reset and de-noise the pull-up node and the output signal terminal under control of a potential at a pull-down node; and a pull-down node control circuit coupled to a first voltage terminal and the pull-down node, and configured to electrically couple the pull-down node to the first voltage terminal under control of the potential at the pull-down node.