Shift Register Unit for OLED Displays with Multi-Stage Inversion Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional shift register units for OLED displays have limited redundancy and are prone to circuit failure due to fluctuations in PMOS transistor threshold voltage, with increased power consumption from large coupling capacitors.
Innovation Solution
A shift register unit design incorporating multiple stages of inversion control circuits, pull-up and pull-down node control circuits, and an output circuit, which eliminates the need for coupling capacitors and enhances tolerance to threshold voltage drifts by maintaining a stable output voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional shift register units are used with PMOS transistors, then the circuit can operate, but the threshold voltage fluctuations cause circuit failure and reduced reliability
Solution Approach 1:
The patent changes the voltage parameters by introducing a pull-up node that can raise the output voltage to a higher level (ELVDD or VGH), and a pull-down node that can lower the output voltage to a lower level (ELVSS or VGL). This creates a larger voltage swing that compensates for threshold voltage drops in PMOS transistors, ensuring the output signal remains within valid logic levels even when transistor thresholds drift due to process variations or aging.
Solution Approach 2:
The patent introduces intermediate control nodes (pull-up control node and pull-down control node) that mediate between the inverter output and the final output signal. These intermediary nodes, controlled by clock signals, actively adjust the voltage level to compensate for threshold voltage fluctuations, acting as a buffer that isolates the circuit from the harmful effects of PMOS threshold drift.
2Reliability
If large coupling capacitors are used to maintain signal integrity, then power consumption increases, but signal stability is improved
Solution Approach 1:
The patent extracts and eliminates the large coupling capacitors from the circuit by replacing their function with active voltage control mechanisms. The pull-up and pull-down control circuits directly adjust the output voltage level without requiring charge storage elements, thereby removing the source of high power consumption while maintaining signal stability through active rather than passive means.
Solution Approach 2:
The patent replaces the passive electrical storage mechanism (capacitors) with an active control mechanism (voltage-controlled switches and voltage sources). Instead of using capacitive charge storage to maintain signal levels, the circuit uses clock-controlled switches to actively drive the output to appropriate voltage levels, substituting a dynamic control system for a static energy storage system.
3Device complexity
If the output voltage range is limited, then the circuit is simpler, but the tolerance to threshold voltage drift is reduced
Solution Approach 1:
The patent introduces dynamic control elements (clock-controlled switches and controllable voltage sources) that actively adjust the output voltage range based on operating conditions. The pull-up and pull-down control nodes dynamically expand or contract the effective voltage swing as needed, allowing the circuit to adapt to threshold voltage drift without requiring a fixed, oversized voltage range that would increase static complexity.
Data Source
AI summary
The present disclosure provides a shift register unit, a driving method, a light emitting control gate driving circuit, and a display apparatus. The shift register unit includes: a light emitting control signal output terminal, a pull-up control node control circuit, N stages of inversion control circuits, a pull-up node control circuit, a pull-down node control circuit, and an output circuit, where N is an integer greater than 1. A first stage of inversion control circuit is configured to invert an input signal. An nth stage of inversion control circuit inverts the input signal under control of an (n−1)th inversion node, where n is an integer and 2≤n≤N.