Shift Register Unit for Narrow Bezel Display Gate Drive
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Solution Overview
Problem
In the field of display technology, achieving high PPI and narrow bezel designs while integrating a gate drive circuit on a TFT array substrate is challenging due to overlapping gate lines, which complicates wiring and increases production costs.
Innovation Solution
A shift register unit with specific input, output, and reset circuits is designed to control node levels and output clock signals, allowing for delayed timing of signals to avoid overlapping gate lines, thereby simplifying the gate drive circuit and reducing the number of shift register units required, thus enabling a narrower bezel and lower production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate lines are arranged in overlapping configuration to drive multiple subpixel rows, then the number of gate lines is reduced, but the wiring complexity increases and production cost increases
Solution Approach 1:
The gate drive circuit is divided into multiple shift register units, each responsible for driving specific gate lines. Each shift register unit contains separate input circuits for different clock signals, allowing independent control and timing adjustment of different gate line groups, thereby reducing wiring complexity while maintaining reduced gate line quantity
Solution Approach 2:
The patent introduces adjustable timing delays for different clock signals (first clock signal and second clock signal) through configurable delay circuits. This dynamic timing adjustment allows optimization of signal transmission timing to avoid overlapping gate line conflicts, reducing wiring complexity while maintaining the reduced number of gate lines
2Adaptability or versatility
If more shift register units are used to drive more subpixel rows, then the driving capability is improved, but the bezel width increases
Solution Approach 1:
Each shift register unit is designed with multi-functionality to drive multiple gate lines through different output paths. The unit can respond to different clock signals (first clock signal and second clock signal) with adjustable timing delays, allowing one shift register unit to effectively drive multiple subpixel rows that would otherwise require separate units, thereby reducing bezel width while maintaining driving capability
Solution Approach 2:
The patent employs adjustable timing delay parameters for clock signals to optimize the driving efficiency of each shift register unit. By configuring different delay values for first and second clock signals, the system maximizes the driving capability of each unit, reducing the total number of units required and consequently reducing bezel width
3Device complexity
If clock signals are transmitted without timing delay to reduce circuit complexity, then the circuit configuration is simplified, but gate line overlapping occurs
Solution Approach 1:
Delay circuits are introduced as intermediary components between clock signal sources and shift register units. These delay circuits adjust the timing of first and second clock signals to prevent gate line overlapping, while maintaining relatively simple overall circuit configuration through standardized delay circuit modules
Data Source
AI summary
A shift register unit, a gate drive circuit, a display panel, a display device and a driving method. The shift register unit includes a first input circuit, a second input circuit, a first output circuit, a second output circuit, a first reset circuit and a second reset circuit. The first input circuit is configured to control a level of a first node in response to a first input signal. The second input circuit is configured to control the level of the first node in response to a second input signal. The first output circuit is configured to output a first clock signal to a first output terminal under a control of the level of the first node. The second output circuit is configured to output a second clock signal to a second output terminal under the control of the level of the first node.