Shift Register Unit for OLED Display Compensation
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Solution Overview
Problem
Existing gate driving circuits face difficulties in simultaneously outputting gate driving signals for display and compensation driving signals for sub-pixel compensation in OLED displays, leading to non-uniform display due to varying threshold voltages of driving transistors.
Innovation Solution
A shift register unit is designed with specific sub-circuits to control node potentials in different phases, allowing for the output of gate driving signals during the display phase and compensation driving signals during the field blanking phase, using a combination of switching transistors and capacitors to manage signal levels and reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a gate driving circuit uses a conventional shift register design, then it can output gate driving signals for display, but it cannot simultaneously output compensation driving signals for sub-pixel compensation
Solution Approach 1:
The patent applies dynamics by making the shift register unit capable of operating in different modes depending on the phase. The circuit dynamically switches between generating gate driving signals during the display phase and compensation driving signals during the field blanking phase, using phase-dependent control signals to activate different functional paths within the same circuit structure.
Solution Approach 2:
The patent implements multi-functionality by designing the shift register unit to perform multiple functions: it can output gate driving signals for normal display operation and compensation driving signals for sub-pixel compensation. The same basic circuit structure serves both purposes by responding to different control conditions in different phases, eliminating the need for separate dedicated circuits.
2Reliability
If the shift register unit outputs both gate driving signals and compensation driving signals, then display quality improves through sub-pixel compensation, but the circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the operation into distinct phases: display phase and field blanking phase. Each phase has dedicated control signals that activate specific circuit paths. This temporal segmentation allows the same physical circuit to produce different signal types at different times, achieving reliable compensation without permanently increasing structural complexity.
Solution Approach 2:
The patent uses phase control signals as intermediaries to mediate between the single shift register unit and the dual output requirements. These control signals act as mediators that direct the circuit's behavior, enabling the same hardware to generate appropriate signals for different purposes without direct structural modification.
3Device complexity
If conventional shift register circuits are used, then the circuit structure remains simple, but threshold voltage variations cause non-uniform display
Solution Approach 1:
The patent applies preliminary action by performing compensation operations during the field blanking phase, which occurs before the next display phase begins. This timing allows compensation signals to be generated and applied in advance, correcting threshold voltage variations before they affect display uniformity, while using the same simple shift register structure.
Data Source
AI summary
The present disclosure provides a shift resister unit, a gate driving circuit, a display device, and a method for controlling a shift register unit. The shift register unit incudes a first input sub-circuit, a first output sub-circuit, a first reset sub-circuit, a second input sub-circuit, and a third input sub-circuit. The first input sub-circuit is configured to change a potential of a first node in a first phase. The first output sub-circuit is configured to output a gate driving signal in the first phase and output a compensation driving signal in a second phase. The first reset sub-circuit is configured to reset the first node. The second input sub-circuit is configured to change a potential of a second node in the first phase and maintain the potential of the second node. The third input sub-circuit is configured to change the potential of the first node in the second phase.