Shift Register Unit for Stable Non-Operating Level in OLED Gate Drivers
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Solution Overview
Problem
Conventional gate driver circuits for OLED displays fail to maintain a stable non-operating level for extended periods, leading to noise interference and poor display quality, especially at low refresh frequencies, due to variations in threshold voltages of driving transistors and leakage currents.
Innovation Solution
A shift register unit comprising an input control circuit, first and second control circuits, an output circuit, and reset circuits, configured to control node levels using multiple clock signals and enable signals, ensuring stable output during detection phases and normal operation during driving phases, thereby reducing noise interference and maintaining a non-operating level for extended periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If conventional gate driver circuits are used to drive OLED displays, then the circuit can operate at low refresh frequencies, but the output cannot maintain a stable non-operating level for extended periods, leading to noise interference and poor display quality
Solution Approach 1:
The gate driver circuit is divided into multiple shift register units, each independently controlling a segment of gate lines. Each unit has dedicated reset circuits that can independently maintain the non-operating level, preventing noise propagation across the entire display and improving output stability during extended detection phases.
Solution Approach 2:
The reset circuits are activated before the detection phase to pre-establish the non-operating level at the output terminals. This preliminary action ensures that the output is already stabilized before detection begins, preventing noise interference and maintaining reliability throughout the extended detection period.
2Reliability
If the gate driver maintains a stable non-operating level during detection phase, then noise interference is reduced, but the circuit complexity increases due to additional reset circuits and control mechanisms
Solution Approach 1:
The reset circuits are merged with the shift register units, sharing common control signals and power supply lines. This integration allows the reset function to be added without proportionally increasing overall circuit complexity, as multiple reset circuits can be controlled by a single enable signal line.
Solution Approach 2:
The reset circuits serve multiple functions: they maintain the non-operating level during detection phases, reset the shift register units after detection, and prevent noise propagation. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity.
3Reliability
If multiple reset circuits are added to each shift register unit, then the output can stably maintain non-operating level, but the manufacturing complexity and cost increase
Solution Approach 1:
Each shift register unit is designed with localized reset circuits that only affect that specific unit's output, allowing for stable non-operating level maintenance without requiring complex global control mechanisms. This modular approach simplifies manufacturing, as each unit can be independently fabricated and tested.
Solution Approach 2:
The reset circuits operate periodically, being activated only during detection phases and deactivated during normal operation. This periodic operation reduces the overall complexity of the reset mechanism, as the circuits do not need to continuously maintain the non-operating level, thereby simplifying manufacturing requirements.
Data Source
AI summary
A shift register unit, a method for driving a shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes: an input control circuit, configured to control a level of the first node; a first control circuit, configured to control a level of the second node; a second control circuit, configured to control the level of the second node under control of a fourth clock signal and an output signal; an output circuit, configured to control a level of the output terminal under control of the level of the first node and the level of the second node; and a first reset circuit, configured to control the level of the output terminal under control of the first enable signal, so as to allow the output terminal to stably output a non-operating level during a detection phase.