Shift Register Unit for OLED Gate Driving Circuit Area Reduction
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Solution Overview
Problem
Current gate driving circuits for OLED displays face challenges in reducing chip area, leading to increased costs and complexity, particularly due to the need for high-resolution and narrow bezel designs, and issues with transistor threshold voltage drift causing leakage currents that affect the normal output of shift register units.
Innovation Solution
A shift register unit comprising a blanking input circuit, display input circuit, output circuit, and coupling circuit is designed to control the level of a control node using a blanking signal, ensuring sufficient charging of a first node during the blanking phase to prevent abnormal outputs, and includes capacitors and transistors to manage clock signals and voltages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate driving circuit is integrated in a GATE IC to reduce area, then chip area is reduced, but transistor threshold voltage drift causes leakage currents affecting normal output
Solution Approach 1:
The patent applies preliminary action by introducing a blanking phase before the display phase, during which the control node is pre-charged to a high level through the blanking input circuit. This pre-charging ensures that when the display phase begins, the control node is already at the required voltage level, compensating for any threshold voltage drift effects and preventing leakage currents from affecting the normal output signal.
Solution Approach 2:
The patent implements beforehand cushioning by using a coupling circuit with a capacitor that couples the control node to the first node. This coupling mechanism provides a voltage buffer that cushions against threshold voltage drift and leakage currents, ensuring stable operation of the shift register unit despite the integrated circuit's miniaturization.
2Reliability
If the shift register unit uses separate blanking and display input circuits, then output signal stability is improved, but device complexity increases
Solution Approach 1:
The patent merges the blanking and display input circuits by having them share common components such as the control node, first node, and output circuit. The blanking input circuit and display input circuit are integrated within the same shift register unit structure, reducing overall device complexity while maintaining separate functional paths for blanking and display phases.
Solution Approach 2:
The patent applies universality by designing the control node and first node to serve multiple functions: they are used during both the blanking phase for pre-charging and during the display phase for normal operation. The output circuit also serves dual purposes by outputting different signals (blanking signal or display signal) based on the phase, reducing the need for separate dedicated circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces chip area by optimizing the shift register unit's operation, preventing leakage currents and ensuring proper output signals, thereby enhancing the performance and efficiency of the gate driving circuit while reducing costs.
Implementation Method 1
the coupling circuit comprises a first capacitor, a first electrode of the first capacitor is connected to a third clock signal terminal to receive a third clock signal and the third clock signal is used as the blanking signal, and a second electrode of the first capacitor is connected to the control node
Data Source
AI summary
A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking input circuit, a display input circuit, an output circuit, and a coupling circuit. The blanking input circuit is configured to input a blanking input signal to a control node and is configured to input a blanking signal to a first node in a blanking phase of one frame; the display input circuit is configured to input a display signal to the first node in a display phase of one frame in response to a first clock signal; and the coupling circuit is electrically connected to the control node and is configured to control, by coupling, a level of the control node in response to the blanking signal.