Shift Register Unit for TFT-LCD Gate Driving Circuit
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Solution Overview
Problem
The existing gate driving circuits for TFT-LCDs are large in size due to the introduction of storage capacitors and large TFTs, which increases the volume of the liquid crystal display and requires more wiring space and control signals, making them inefficient.
Innovation Solution
A shift register unit comprising an input unit, an output unit, a pull-up unit, a pull-down control unit, and a pull-down unit, which eliminates the need for storage capacitors and large TFTs by using a TFT with a thick depletion layer to maintain stable voltage and reduce the size of the shift register unit, thereby reducing the overall volume of the liquid crystal display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a storage capacitor and large TFT are introduced to maintain stable output voltage, then the stability of the output signal is improved, but the area of the shift register unit increases
Solution Approach 1:
The patent removes the storage capacitor from the traditional shift register unit structure. Instead of using a separate capacitor to maintain voltage stability, the invention uses a specially designed TFT with a thick depletion layer that inherently provides stable voltage output without requiring additional capacitive elements, thereby eliminating the need for extra wiring space.
Solution Approach 2:
The patent changes the physical parameters of the TFT by increasing the thickness of the depletion layer. This parameter change allows the TFT to maintain stable output voltage through its inherent electrical characteristics rather than requiring external capacitive components, thus achieving voltage stability while reducing the overall circuit area.
2Adaptability or versatility
If six control signals are used to achieve output and reset functions, then the functionality of the shift register unit is improved, but the device complexity increases
Solution Approach 1:
The patent designs the shift register unit to perform both output and reset functions using a reduced set of control signals. The circuit structure is optimized so that fewer signals (four instead of six) can control multiple functions through clever use of the TFT switching characteristics and signal timing, reducing wiring complexity while maintaining full functionality.
Solution Approach 2:
The patent combines the control functions into fewer signals by merging the roles of separate control lines. The reduced set of four control signals is designed to handle both output control and reset operations that traditionally required six separate signals, thereby simplifying the device while maintaining adaptability.
3Reliability
If the size of TFT M3 is increased to reduce couple capacitance influence, then the stability of output signal is improved, but the volume of liquid crystal display increases
Solution Approach 1:
The patent changes the depletion layer thickness parameter of the TFT to achieve stable output. By optimizing this physical parameter, the circuit achieves voltage stability without needing to increase the TFT's overall size or require large wiring spaces, thus avoiding an increase in the liquid crystal display volume.
Solution Approach 2:
The patent applies a localized structural modification to the TFT by creating a thick depletion layer in a specific region of the transistor. This local quality change allows the TFT to provide stable voltage output through its enhanced electrical characteristics without requiring an overall increase in device size, thereby maintaining compact display volume.
Data Source
AI summary
A shift register unit and a gate driving circuit are configured to reduce size of the shift register unit and meanwhile to provide a stable output signal. The shift register unit includes: an input unit configured to supply an input signal to an output unit in response to the input signal; the output unit configured to supply a first clock signal to an output terminal in response to a voltage at the first node; a pull-up unit configured to supply the first clock signal to the first node in response to the voltage at the first node; a pull-down control unit configured to supply the first clock signal, a second clock signal and a negative voltage of a power supply to the pull-down unit in response to the first clock signal, the second clock signal and the voltage at the first node; and the pull-down unit configured to supply the negative voltage of the power supply to the first node and the output terminal in response to a voltage at the second node.