Shift Register Unit for Narrow Frame OLED Displays
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Solution Overview
Problem
In OLED display devices, the variation in threshold voltages of drive transistors due to manufacturing limitations and temperature drift leads to non-uniform displays and leakage currents, requiring complex pixel circuits with compensation functions, which increases the area occupied by gate drive circuits, hindering the implementation of narrow frames.
Innovation Solution
A shift register unit comprising an input circuit, an output circuit, and a control circuit, which simultaneously provides multiple gate drive signals required by pixel circuits, featuring a simple circuit structure that simplifies the gate drive circuit and facilitates narrow frame implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex pixel circuits with compensation functions are used to address transistor voltage variations, then display uniformity is improved, but the area occupied by gate drive circuits increases
Solution Approach 1:
The patent combines multiple gate drive signals (ELVDD, ELVSS, and scanning signals) into a single integrated shift register unit. The output circuit integrates multiple signal output terminals that can simultaneously provide different gate drive signals, merging what would traditionally require separate circuits into one compact unit, thereby reducing overall gate drive circuit area while maintaining display uniformity through compensation functions
Solution Approach 2:
The shift register unit is designed with multi-functionality, where the output circuit can simultaneously provide multiple types of gate drive signals to different pixel circuits. The circuit structure allows it to function as both a scanning signal generator and a voltage compensation provider, enabling one circuit to perform multiple roles that would traditionally require separate dedicated circuits
2Manufacturing precision
If complex pixel circuits with compensation functions are used to address transistor voltage variations, then display uniformity is improved, but device complexity increases
Solution Approach 1:
The patent merges the compensation function into the gate drive circuit itself rather than requiring separate compensation circuits within each pixel. The shift register unit integrates voltage division control sub-circuits that automatically generate compensated voltage signals, combining scanning and compensation functions in one unit, thereby reducing pixel circuit complexity while maintaining display uniformity
3Area of stationary object
If the gate drive circuit area is reduced to enable narrow frames, then assembly cost is reduced, but the ability to provide multiple gate drive signals may be compromised
Solution Approach 1:
The output circuit is designed with multiple signal output terminals (first, second, and third signal output terminals) that can simultaneously provide different gate drive signals including ELVDD, ELVSS, and scanning signals. This multi-functional design allows the compact circuit to maintain full signal provision capability while occupying reduced area, enabling narrow frame implementation without compromising adaptability
Solution Approach 2:
The patent utilizes vertical integration and multi-layer circuit design to provide multiple gate drive signals in a compact footprint. By stacking circuit functions vertically and using multiple signal output terminals, the design achieves high signal diversity in a reduced planar area, enabling narrow frames while maintaining full gate drive signal capability
Data Source
AI summary
A shift register unit, a method for driving a shift register unit, a gate drive circuit, and a display device are disclosed. A shift register unit includes an input circuit, an output circuit, and a first control circuit. The input circuit controls a level of a first node in response to an input signal. The output circuit outputs at least one clock signal of at least one clock signal terminal to at least one signal output terminal under the control of the level of the first node, and outputs a level of a second node to at least one of the at least one signal output terminal in the case where the first node is at a non-operating potential. The first control circuit controls the level of the second node in response to the level of the first node.