Shift Register Clock and Power Gating for Unused Upper Bits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional shift registers consume energy unnecessarily due to active flip-flops for unused upper bits, even when the data width requires only lower bits, leading to inefficiency in computation.
Innovation Solution
A shift register design that includes a gating circuit and power gating circuit to disable unused upper flip-flops based on input data, allowing the register to enter a low power mode by decoupling them from the clock and power supply when not needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all flip-flops in the shift register are kept active to ensure complete data storage capability, then the shift register can handle any data width, but unused flip-flops consume unnecessary energy
Solution Approach 1:
The shift register dynamically adjusts its operational state by transitioning between active and disabled states based on actual data width requirements. The control circuit monitors the most significant bit position and dynamically enables or disables corresponding flip-flops, making the system adaptable rather than static.
Solution Approach 2:
Different flip-flops in the shift register are treated differently based on their position and usage. Flip-flops corresponding to used bit positions maintain full functionality, while those corresponding to unused upper bits are disabled. This local differentiation optimizes power consumption without compromising overall data storage capability.
2Use of energy by moving object
If unused upper flip-flops are disabled to reduce power consumption, then energy efficiency improves, but the shift register must continuously monitor data width to determine which flip-flops to disable
Solution Approach 1:
The control circuit automatically determines which flip-flops to disable by monitoring the most significant bit position of the input data. The system serves itself by using the data characteristics to control its own power state without requiring external intervention or complex manual configuration.
Solution Approach 2:
The control circuit uses feedback from the data input signals, specifically monitoring the most significant bit position, to automatically adjust the enable/disable state of flip-flops. This feedback mechanism allows the system to adapt its power consumption based on actual data width requirements.
3Loss of energy
If the shift register enters low power mode by disabling unused flip-flops, then energy is conserved, but additional gating circuits are required to control the enable/disable functionality
Solution Approach 1:
The patent extracts and isolates the control functionality into a separate control circuit that monitors data width and generates enable/disable signals. This extracted control mechanism manages the gating functions independently, allowing the main shift register functionality to remain focused on data storage and transmission.
Solution Approach 2:
The control circuit serves multiple functions: it monitors the most significant bit position, determines data width, generates control signals for multiple flip-flops, and manages the transition between active and low power modes. This multi-functional approach reduces the need for separate dedicated circuits for each control task.
Data Source
AI summary
The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.