Shift-Register PWM Circuit With Variable Clock Durations
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Solution Overview
Problem
Existing methods for generating PWM signals are inefficient in terms of data rate and do not effectively utilize the information density of shift registers, leading to increased parasitic current spikes and crosstalk, particularly when controlling light-emitting and display arrangements.
Innovation Solution
A method and circuit using a shift register with clock-controlled register units, where the duration of clock signals varies within a cycle, allowing for weighted logic values to be output as a PWM signal, increasing information density and reducing the number of switching operations, thereby minimizing parasitic current spikes and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If conventional PWM signal generation methods are used with constant clock duration, then the circuit operation is simple, but the information density of the shift register is not effectively utilized and parasitic current spikes increase
Solution Approach 1:
The patent applies dynamics by varying the duration of clock pulses within a cycle according to a dynamic pattern (e.g., exponentially increasing or decreasing durations). This dynamic clocking scheme allows the shift register to encode more information in fewer clock cycles, increasing information density utilization while reducing the number of switching operations that generate parasitic current spikes
Solution Approach 2:
The patent changes the time parameter of clock pulses by varying their durations within a cycle. Instead of using constant duration clocks, the system uses clocks with progressively changing durations (e.g., 1ms, 2ms, 4ms, 8ms pattern), which transforms how information is encoded in the shift register and reduces the total number of clock cycles needed, thereby reducing parasitic effects
2Adaptability or versatility
If the number of register units is increased to achieve more duty cycles, then the number of controllable duty cycles increases, but the device complexity and data rate requirements increase
Solution Approach 1:
By implementing dynamic clock durations, the system achieves higher adaptability with fewer register units. The varying clock patterns enable the same number of register units to produce more distinct duty cycle combinations, effectively increasing system versatility without adding more hardware components
Solution Approach 2:
The patent uses periodic clock cycles with varying internal patterns to generate different duty cycles. By repeating cycles with different clock duration patterns (e.g., ascending vs. descending duration sequences), the system multiplies the number of achievable duty cycles from the same register units, reducing device complexity
3Productivity
If the data rate is increased to improve PWM signal generation efficiency, then the signal update speed improves, but parasitic current spikes and crosstalk increase
Solution Approach 1:
The dynamic clocking scheme improves PWM generation efficiency by encoding more information per clock cycle, reducing the total number of switching operations required. This reduces both the data rate burden and the frequency of parasitic current spikes, thereby reducing crosstalk while maintaining or improving overall efficiency
Solution Approach 2:
The patent converts the potential harm of clock signal switching into a benefit by using varied clock durations to encode information more densely. This reduces the total number of switching events needed, thereby reducing parasitic effects while achieving the same or better signal generation efficiency
Data Source
AI summary
A circuit for generating a PWM signal includes a shift register having a plurality of clock-controlled register units. Each clock-controlled register unit has an input and an output. The circuit also includes a write unit configured to set the outputs of the register units each to a designated logical value. The circuit further includes a clock generator configured to drive the register units with a common clock signal. The register units are connected in series. The shift register is configured to output the PWM signal at an output contact. The PWM signal is a chronological sequence of the logical values set in the register units, the PWM signal assumes each of the logical values with the duration of one clock of the clock signal, the clock signal is cyclic, during one cycle the duration of successive clocks changes, and the clock signal is identical per cycle.