Shift Register Set-Node Voltage Stabilization Against Transistor Drift

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Solution Overview

Problem

The large negative drift of transistors in shift register units due to voltage impact during operation reduces their service life.

Innovation Solution

A shift register unit with a voltage adjusting circuit that includes capacitors to stabilize the voltage of set nodes in response to clock signal terminals, reducing the negative drift and extending transistor life.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a shift register unit operates with standard voltage levels, then it achieves normal switching functionality, but large negative drift occurs in transistors reducing their service life

Engineering Contradiction:
Improvetransistor service lifeVSAvoidvoltage impact on transistor
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The voltage adjusting circuit proactively modifies the voltage level before it reaches the transistor, preventing the harmful voltage impact before it occurs. By adjusting the voltage in advance based on clock signal timing, the circuit ensures transistors operate at safe voltage levels throughout their service life.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The voltage adjusting circuit acts as an intermediary between the clock signal terminal and the transistor, mediating the voltage levels. This intermediate circuit buffers and conditions the voltage, protecting the transistor from direct exposure to harmful voltage spikes while maintaining proper switching functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If voltage adjusting circuit is added to reduce negative drift, then transistor service life is prolonged, but device complexity increases

Engineering Contradiction:
Improvetransistor service lifeVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The voltage adjusting circuit is merged with the existing shift register unit structure, sharing common elements such as the clock signal terminal and integrating seamlessly with the set node. This combination approach adds voltage adjustment functionality without creating a completely separate complex subsystem.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The voltage adjusting circuit is designed to serve multiple functions: it adjusts voltage levels, reduces negative drift, and protects transistor reliability. By making this circuit multi-functional, the patent avoids needing separate dedicated circuits for each function, thereby reducing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The capacitors effectively mitigate voltage fluctuations at the set nodes, prolonging the service life of the transistors and ensuring stable operation of the shift register unit.

Implementation Method 1

a first terminal of the first capacitor is coupled to the first clock signal terminal, and a second terminal of the first capacitor is coupled to the pull-up node

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20260011281A1Shift register unit, gate driving circuit, and display device
Publication Date: 2026.01.08 HEFEI BOE ZHUOYIN TECH CO LTD
  • US20260011281A1 patent drawing
  • US20260011281A1 patent drawing
  • US20260011281A1 patent drawing

AI summary

A shift register unit, a gate driving circuit and a display device are disclosed. The shift register unit includes a shift register and a voltage adjusting circuit. The voltage adjusting circuit is coupled to a set node of the shift register. In a working process, the voltage adjusting circuit is configured to adjust a voltage of the set node in response to a signal of a first clock signal terminal.