Shift Register Voltage Drop Prevention in Touch Displays
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Solution Overview
Problem
Touch display apparatuses experience voltage drops during transition from touch to display periods due to leakage currents, leading to abnormal image display, as the gate driver's shift register fails to maintain the required voltage levels.
Innovation Solution
Incorporating a shift register with cascade-connected unit circuits that include input, output, and pull-up transistors, along with a reset module, to generate shifted pulse signals with a specified phase and insert blank periods between adjacent pulse signals, ensuring the output terminal voltage is maintained at a high level using a pull-up transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate driver operates during touch period with driving transistor remaining on, then touch operation is enabled, but voltage drops due to leakage current cause abnormal image display
Solution Approach 1:
The patent applies dynamics by making the gate driver operational state changeable between display period and touch period. During touch period, the gate driver is dynamically switched to a stopped state where output signals are suspended, preventing voltage drops caused by leakage current while maintaining touch functionality. This dynamic state transition resolves the contradiction between enabling touch operation and maintaining image display quality.
Solution Approach 2:
The patent implements preliminary anti-action by proactively stopping the gate driver before voltage drops can occur during touch period. By suspending the output signals in advance, the system prevents the harmful effect of leakage current-induced voltage drops that would otherwise cause abnormal image display, thus maintaining image quality while enabling touch operation.
2Duration of action of stationary object
If the shift register continues outputting scanning signals during touch period, then continuous scanning is maintained, but voltage levels drop below specified threshold causing display abnormalities
Solution Approach 1:
The patent applies periodic action by dividing the operation into distinct display period and touch period. During touch period, the gate driver enters a stopped state with periodic suspension of scanning signals. This periodic interruption prevents continuous voltage drops while maintaining the ability to resume scanning when touch operation is complete, thus preserving voltage level precision during critical periods.
Solution Approach 2:
The patent implements preliminary action by stopping the gate driver output signals before voltage drops can occur during touch period. By proactively suspending the scanning signals in advance, the system prevents voltage levels from falling below the specified threshold, thereby maintaining voltage precision while still enabling touch functionality.
3Adaptability or versatility
If the driving transistor remains on during touch period, then touch input is enabled, but leakage current causes voltage decrease and turning-on voltage increase
Solution Approach 1:
The patent applies the taking out principle by extracting the gate driver output function during touch period. By suspending the scanning signal output while maintaining the driving transistor on for touch input, the system separates the touch input function from the scanning output function. This extraction simplifies voltage control by eliminating the conflicting requirements of maintaining both continuous scanning and touch input capability.
Data Source
AI summary
A shift register driving a touch display device generates shifted pulse signals shifted by a specified phase. The shift register includes unit circuits connected in multiple stages. Each unit circuit includes an output terminal, an input transistor, an output transistor, and a pull-up transistor. The input transistor is controlled by a first control signal and outputs a high-level voltage to a first node based on the value of a trigger signal. The output transistor outputs the shifted pulse signal, which is synchronous with a clock control signal, based on the value of the high-level voltage of the first node. A blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit. After the blank period, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage.