Shift Register Voltage Margin Boost for High Temperature Stability
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Solution Overview
Problem
In high temperature environments, the increased carrier mobility of thin film transistors in gate driving circuits leads to voltage drops at the pulling-down node, causing a splash screen problem due to insufficient voltage margin, which prevents correct clock signal output and normal operation of pixel transistors.
Innovation Solution
A shift register design with a voltage regulating sub-circuit that includes transistors and capacitors (2T1C) to boost the gate voltage of transistors, reducing internal resistance and increasing the voltage margin at the pulling-down node, thereby maintaining operation even in high temperature conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thin film transistors operate in high temperature environment, then carrier mobility increases, but voltage margin at pulling-down node decreases causing splash screen problem
Solution Approach 1:
The patent changes the electrical parameters of the transistor by adjusting its aspect ratio (width-to-length ratio). By increasing the aspect ratio of the transistor at the pulling-down node, the patent compensates for the increased carrier mobility at high temperatures, thereby maintaining sufficient voltage margin and preventing the splash screen effect.
2Reliability
If transistor aspect ratio is increased to maintain voltage margin, then internal resistance decreases, but device area increases
Solution Approach 1:
The patent applies local quality by selectively adjusting the aspect ratio of specific transistors at critical nodes (pulling-down node and pulling-down controlling node) rather than uniformly scaling all transistors. This targeted approach maintains voltage margin where needed while minimizing the overall area increase of the shift register circuit.
Data Source
AI summary
Embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an inputting sub-circuit, an outputting sub-circuit, a resetting sub-circuit, a pulling-down sub-circuit, a pulling-down controlling sub-circuit, and a voltage regulating sub-circuit. The voltage regulating sub-circuit is coupled to a pulling-down node, a pulling-down controlling node, a second clock signal terminal, a third clock signal terminal, a first voltage signal terminal and a second voltage signal terminal, and is configured to regulate a voltage at the pulling-down controlling node based on a first voltage signal from the first voltage signal terminal and a second voltage signal from the second voltage signal terminal, under a control of the second clock signal from the second clock signal terminal, a third clock signal from the third clock signal terminal, and the voltage at the pulling-down node.