Shift Register Circuit Layout for Longer Output Voltage Period
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Solution Overview
Problem
Existing shift register designs face challenges in extending the output voltage period, reducing the number of transistors, minimizing power consumption, and optimizing layout area and manufacturing steps.
Innovation Solution
A semiconductor device with a novel circuit configuration using first to fourth transistors, where the transistors are connected in a specific manner to enhance the output voltage period, reduce transistor count, and optimize power consumption and layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If transistor M2 is turned on to output voltage VOFF, then voltage output is achieved, but the output period is short and transistor M4 is also turned on causing malfunction
Solution Approach 1:
The patent divides the voltage output control into separate, independent transistor operations. Instead of having M2 and M4 share a gate connection that causes simultaneous activation, the circuit is segmented so that each transistor can be independently controlled to output VOFF during different phases, preventing the malfunction while extending the overall output period.
Solution Approach 2:
The patent implements dynamic control of transistor switching sequences. By dynamically adjusting which transistor (M2 or M4) is active at different times rather than having them simultaneously controlled, the circuit achieves extended voltage output periods while maintaining proper shift register operation through phased activation.
2Duration of action of moving object
If two transistors Q53 and Q56 are used to output voltage VOFF, then voltage output is achieved, but the number of transistors increases
Solution Approach 1:
The patent makes existing transistors in the shift register perform dual functions. The same transistors that perform shifting operations also output the VOFF voltage during appropriate phases, eliminating the need for dedicated additional transistors and reducing overall device complexity while maintaining extended output periods.
Solution Approach 2:
The patent merges the voltage output function with the existing shift register transistor operations. By combining multiple functions into the same transistor components, the circuit achieves extended voltage output without increasing the transistor count, thereby reducing device complexity.
3Duration of action of moving object
If more transistors are used to extend output period, then voltage output duration increases, but manufacturing steps and layout area increase
Solution Approach 1:
The patent designs the circuit so that existing transistors automatically provide the VOFF output function during their normal operation cycles. The transistors serve themselves by performing both shifting and voltage output functions, eliminating the need for additional manufacturing steps dedicated to creating separate voltage output components.
Solution Approach 2:
The patent combines multiple circuit functions into existing transistor structures, thereby achieving extended output periods without adding components that would require additional manufacturing steps. This merging approach simplifies the fabrication process while maintaining enhanced functionality.
4Duration of action of moving object
If more transistors are used to extend output period, then voltage output duration increases, but layout area increases
Solution Approach 1:
The patent makes existing transistors perform multiple functions including both shift register operation and voltage output. This multi-functionality allows the circuit to achieve extended output periods without adding additional transistor components, thereby maintaining a compact layout area.
Solution Approach 2:
The patent merges the voltage output function with existing transistor structures, eliminating the need for separate components that would increase layout area. By combining functions into existing elements, the circuit achieves extended output duration while maintaining space efficiency.
Data Source
AI summary
To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.