Shift Register Low Level Voltage Stability via Segmented Switching
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Solution Overview
Problem
The low level voltage signal outputted by shift registers in display panels is unstable due to fluctuations caused by clock signals and parasitic capacitance, leading to inconsistent performance in gate driving circuits.
Innovation Solution
A shift register design that includes a first and second switch device configuration, where the first switch device writes a cut-off level of the power supply voltage into a second node during low level output phases, and the second switch device is switched off to prevent signal transmission to the first node, ensuring a stable low level voltage output by isolating the clock signal terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the shift register uses conventional switch device configuration connected to clock signal terminal, then the circuit can operate with clock signaling, but the low level voltage output becomes unstable due to clock signal fluctuations and parasitic capacitance
Solution Approach 1:
The patent divides the switch device into two separate switch devices (first switch device and second switch device) with distinct functions. The first switch device controls the power supply voltage signal terminal to the second node, while the second switch device controls the clock signal terminal to the first node. This segmentation isolates the clock signal fluctuations from affecting the power supply voltage, thereby stabilizing the low level output without requiring overly complex interconnected switching arrangements.
Solution Approach 2:
The patent introduces a second node as an intermediary between the power supply voltage signal terminal and the first node. The first switch device writes the cut-off level of the power supply voltage into this intermediate second node, which then influences the first node. This intermediary structure prevents direct coupling between clock signal variations and the power supply voltage at the output node, stabilizing the low level output while maintaining manageable circuit complexity.
2Productivity
If the switch devices are connected to the clock signal terminal to enable clocked operation, then the shift register can function as intended, but signal fluctuations from the clock terminal affect the stability of the output voltage
Solution Approach 1:
The patent segments the switching functions so that one switch device (first switch device) is dedicated to controlling power supply voltage signals independent of the clock terminal, while another switch device (second switch device) handles clock signal control. This functional segmentation allows the shift register to maintain its clocked operation capability while preventing clock signal fluctuations from degrading output voltage stability.
Solution Approach 2:
The patent extracts the power supply voltage control function from the clock signal path by using a separate first switch device that is not connected to the clock signal terminal. This extracted power supply control path writes the cut-off level into an intermediate second node, isolating it from clock signal fluctuations and maintaining stable low level output while preserving shift register functionality.
3Reliability
If the first switch device writes cut-off level into the second node during low level output phase, then the low level voltage stability is improved, but the circuit requires additional switching control mechanisms
Solution Approach 1:
The patent implements preliminary action by having the first switch device write the cut-off level of the power supply voltage into the second node in advance during the low level output phase. This pre-establishment of the cut-off level in the intermediate second node ensures that when the output is needed, the stable reference level is already in place, improving low level voltage stability without requiring complex real-time control mechanisms during the actual output phase.
Data Source
AI summary
A shift register, a method for driving a shift register, a gate driving circuit and a display panel are provided. The shift register includes: a first output device, where a control terminal thereof is electrically connected to a first node, a first terminal thereof is electrically connected to a first clock signal terminal, and a second terminal thereof is electrically connected to an output terminal of the shift register; a first node control device including a first switch device and a second switch device, where the first switch device is electrically connected to the first node, a first power supply voltage signal terminal and a second node, and the second switch device is electrically connected to the second node, the first power supply voltage signal terminal and the first node.