Shift Register Voltage Stabilizing Device for Low Frame Rate Stability

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Solution Overview

Problem

The high power consumption of display devices due to low frame rates leads to instability in shift register circuits, causing flickering and poor display quality due to large leakage currents from PMOS transistors made from low temperature poly-silicon material.

Innovation Solution

Incorporating a first voltage stabilizing device with a small leakage current into the shift register circuit, which is controlled by a clock signal to manage the potential of nodes, ensuring stable output even at low frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If PMOS transistors made from low temperature poly-silicon material are used in the shift register circuit, then the device can operate at low frame rates to reduce power consumption, but large leakage currents cause instability and flickering

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal stability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

A voltage stabilizing device is introduced as an intermediary component between the clock signal terminal and the control terminal of the output device. This stabilizing device mediates the clock signal to prevent leakage current from affecting the control signal stability, allowing the circuit to operate reliably at low frame rates while maintaining signal integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Use of energy by moving object

If the frame rate is reduced to drive pixels at low speed for power savings, then power consumption decreases, but the data update period becomes longer and leakage current effects become more pronounced

Engineering Contradiction:
Improvepower consumptionVSAvoiddata update period
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The voltage stabilizing device performs preliminary stabilization of the control signal before it is used to drive the output device. By pre-stabilizing the signal and preventing leakage current effects in advance, the circuit maintains reliability even during the extended data update period associated with low frame rate operation.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If a voltage stabilizing device with small leakage current is added to the shift register circuit, then leakage current is reduced and signal stability is improved, but the device complexity increases

Engineering Contradiction:
Improvesignal stabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shift register circuit is segmented into functional blocks, with the voltage stabilizing device as a distinct segment between the clock signal terminal and the output device. This segmentation isolates the leakage current problem to a specific component, allowing the rest of the circuit to maintain its original simplicity while achieving improved reliability.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11308907B2Shift register and driving method of shift register, gate driving circuit and display panel and device
Publication Date: 2022.04.19 WUHAN TIANMA MICRO ELECTRONICS CO LTD
  • US11308907B2 patent drawing
  • US11308907B2 patent drawing
  • US11308907B2 patent drawing

AI summary

Provided are a shift register and a driving method of a shift register, a gate driving circuit and a display panel and device. The shift register includes a first power signal input terminal, a second power signal input terminal, a first signal output terminal, a first node control device, a first output device, a first voltage stabilizing device and a first clock signal terminal, where a first terminal of the first voltage stabilizing device is electrically connected to an output terminal of the first node control device at a first node, a second terminal of the first voltage stabilizing device is electrically connected to a first control terminal of the first output device at a second node, and a control terminal of the first voltage stabilizing device is electrically connected to the first clock signal terminal.