Shift Register Circuit Voltage Stress Management
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Solution Overview
Problem
High-definition display apparatuses with high pixel density face increased wiring capacitance and shortened horizontal periods, leading to high voltage stress on transistors, which decreases the reliability of semiconductor devices in scan line driver circuits.
Innovation Solution
A semiconductor device with a specific circuit configuration including multiple transistors and capacitors that manage clock signals and control potentials to reduce voltage stress on transistors, ensuring reliable operation by minimizing the duration of voltage stress application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel density is increased to achieve high-definition display, then display resolution is improved, but wiring capacitance increases causing voltage stress on transistors
Solution Approach 1:
The patent applies dynamic voltage control by switching between normal driving voltage and boosted voltage based on operational requirements. The voltage boosting circuit dynamically adjusts the scan line voltage to compensate for capacitance effects without continuously applying high voltage, thereby reducing stress on transistors while maintaining display resolution performance.
Solution Approach 2:
The patent changes the voltage parameter dynamically by introducing a voltage boosting mechanism that temporarily increases the scan line voltage potential. This parameter change allows the system to overcome wiring capacitance effects during critical periods while returning to normal voltage levels during other periods, reducing cumulative voltage stress on transistors.
2Speed
If current flowing in scan line is increased to charge scan line faster, then charging speed is improved, but voltage stress on transistors increases
Solution Approach 1:
The patent implements periodic voltage boosting where the scan line voltage is enhanced only during specific periods when charging is required, rather than continuously. This periodic action allows fast charging during critical intervals while minimizing the duration of high voltage stress on transistors, thus improving charging speed without proportionally increasing reliability risks.
Solution Approach 2:
The voltage boosting circuit performs preliminary voltage enhancement before data writing operations to ensure scan lines are properly charged and ready for signal transmission. This preliminary action prevents the need for continuous high current flow during normal operation, reducing transistor stress while maintaining charging performance.
Data Source
AI summary
Provided is a highly reliable semiconductor device. The present invention relates to a shift register circuit including a plurality of stages of sequential circuits. An output signal of a sequential circuit is input to a sequential circuit in the subsequent stage. Before a sequential circuit outputs a signal and after the sequential circuit outputs the signal, the potential of a gate of a transistor included in the sequential circuit is changed in accordance with a clock signal so as to avoid voltage stress application between the gate and a source of the transistor for a long time. The shift register circuit can be applied to a scan line driver circuit of a display apparatus, for example.