Shift-Register Waveform Generator for Dense Multi-Channel Ultrasound
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Solution Overview
Problem
Existing waveform generators face limitations in flexibility, memory efficiency, and signal routing due to the arrangement of memory arrays and contact pins, especially in applications requiring a large number of channels, such as ultrasonography.
Innovation Solution
A waveform generator utilizing a two-dimensional shift register made of parallel-operated unidimensional shift registers, which allows for compressed waveform representation and storage, eliminating the need for conventional random access memory and reducing the complexity of signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory arrays are used to store waveform parameters, then waveform flexibility and design freedom are improved, but device complexity and signal routing complexity increase due to arrangement of contact pins and connection lines
Solution Approach 1:
The patent extracts the waveform storage function from conventional random access memory and implements it using shift registers integrated directly into the waveform generator circuitry. This eliminates the need for separate memory arrays with complex contact pin arrangements and connection lines, thereby reducing signal routing complexity while maintaining waveform flexibility.
Solution Approach 2:
The patent merges the waveform storage and generation functions into a single integrated circuit block. By combining the shift register-based memory with the waveform generation logic in one unit, the design eliminates the need for separate memory arrays and their associated complex routing infrastructure.
2Adaptability or versatility
If small blocks of memory are used for each channel, then independent waveform storage per channel is achieved, but area occupation efficiency deteriorates due to dedicated circuitry requirements
Solution Approach 1:
The patent implements a universal shift register structure that can serve multiple channels simultaneously. Rather than dedicating separate memory blocks with full decoder and control circuitry to each channel, a single multi-functional shift register system serves all channels, dramatically improving area efficiency while maintaining independent waveform storage capability.
Solution Approach 2:
The patent segments the waveform data into serial bits that are shifted through the register, allowing compact storage. This segmentation approach enables multiple channels to share the same physical memory resources by time-multiplexing the shifted data, reducing the total area required compared to dedicated memory blocks.
3Quantity of substance
If conventional random access memory is used, then waveform parameters can be stored, but device complexity increases due to address managers and decoding circuitry
Solution Approach 1:
The patent replaces the mechanical/electrical addressing system of conventional RAM (with address buses, decoders, and control logic) with a simpler serial shift register mechanism. Waveform parameters are loaded once into the shift register and then automatically output in sequence without requiring complex addressing or decoding circuitry during operation.
Data Source
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AI summary
A waveform generator includes: a system control unit (2) and a plurality of channels, (3.1, ..., 3.N) controlled by the system control unit (2) and configured to supply driving signals (V1, ..., VM) for driving a respective one of an array of transducers (5.1, ..., 5.N). Each channel includes: a sequential access memory (10) having a plurality of rows, each containing instruction words (W) configured to generate a respective step of a waveform, and a memory output (10a) defined by an output row at a fixed location, the waveform being defined by a block of instruction words (W). Each channel also includes an internal control unit (12), configured to sequentially move the content of the sequential access memory (10), based on the instruction word (W) currently at the memory output (10a), so that sequences of instruction words (W) are provided at the output row (10a).