Shift Register Wiring Complexity Reduction
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Solution Overview
Problem
Traditional image processing technologies face challenges in balancing versatility and power efficiency, with general-purpose processors consuming more energy due to finer grained data structures and custom-designed circuits offering limited tasks with improved power efficiency but reduced versatility.
Innovation Solution
A shift register design that reduces wiring complexity by physically laying out cells in a non-logical order, supporting multiple shift amounts in a single cycle using a combination of shifting and straight-through unit cells, and implementing a bi-directional shift register to minimize wiring resources while maintaining efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If cells are laid out in strict logical order in a shift register, then the logical sequence is simplified, but the wiring length and complexity increase significantly
Solution Approach 1:
The shift register is divided into multiple banks of cells, where each bank contains cells with similar shift destinations. This segmentation allows cells to be physically grouped by function rather than logical sequence, reducing wiring length while maintaining operational integrity through bank-specific control signals.
Solution Approach 2:
Different regions of the shift register (different banks) are optimized for different shift amounts. Cells in each bank are configured with local wiring patterns optimized for their specific shift destination, allowing short wiring lengths locally while supporting varied shift operations globally across all banks.
2Adaptability or versatility
If a shift register supports multiple shift amounts in a single cycle, then versatility is improved, but wiring complexity and resource requirements increase
Solution Approach 1:
The shift register banks are designed to support multiple shift amounts (1, 2, 3, 4) using the same physical infrastructure. Each bank can be configured to perform different shift operations by selecting which cells within the bank are active, allowing a single set of wiring resources to serve multiple functions.
Solution Approach 2:
The shift register employs dynamic cell enabling where cells within each bank can be selectively activated or deactivated based on the required shift amount. This dynamic configuration allows the same physical wiring to support variable shift operations without requiring dedicated wiring for each shift amount.
3Use of energy by moving object
If larger blocks of data are processed by custom designed circuits, then power consumption per unit of data is reduced, but the set of tasks the processor can perform becomes limited
Solution Approach 1:
The processing array is divided into multiple banks that can be independently configured and activated. This segmentation allows the system to process large blocks of data efficiently when needed while maintaining the ability to activate only the necessary banks for smaller or varied tasks, thus balancing power efficiency with versatility.
Solution Approach 2:
The system dynamically configures which banks and cells are active based on the specific processing task requirements. This dynamic adaptation allows the custom-designed circuitry to optimize power consumption for each task while maintaining access to a wide range of processing capabilities through different configuration patterns.
Data Source
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AI summary
A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.