Bidirectional Shift Register Without Inverters for Stable Low-Power Output
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Solution Overview
Problem
Conventional bidirectional shift registers exhibit high power consumption due to inverter structures and clock coupling effects, leading to unstable output waveforms.
Innovation Solution
A shift register design with serially connected stages, utilizing MOS thin film transistors and capacitors to manage clock signals and supply voltages, eliminating the need for inverter structures and reducing power consumption by coupling the drain of the outputting transistor to a high voltage, thus minimizing coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inverter structures are used in shift register stages, then signal level restoration is improved, but power consumption increases
Solution Approach 1:
The patent removes the inverter structure from the shift register stage, extracting the problematic component that caused high power consumption. The output transistor's drain is directly connected to the high voltage line, eliminating the need for an inverter while maintaining signal integrity through the capacitive coupling mechanism.
2Productivity
If clock signals are applied to transistor gates for signal transmission, then signal transfer is improved, but coupling effects cause output waveform instability
Solution Approach 1:
The patent introduces a capacitor as an intermediary element between the transistor source and the output node. This capacitor couples the output signal without direct clock signal interference, acting as a mediator that transfers the signal while blocking the harmful coupling effects from the clock lines.
3Ease of operation
If multiple transistors are connected between output terminal and power supply for discharge function, then discharge capability is improved, but device complexity increases
Solution Approach 1:
The patent combines the discharge function with the existing transistor structure by controlling the output transistor's gate voltage through clock signals. Instead of adding separate discharge transistors, the solution merges the discharge capability into the output transistor's operation, reducing overall device complexity.
Data Source
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AI summary
A shift register comprising a plurality of shift register stages {SN}, N=1, 2, ..., M, M being a nonzero positive integer. Each of the plurality of shift register stages, SN, comprises a first input, a second input, a third input for receiving a first clock signal CK, a fourth input for receiving a second clock signal XCK, an output for providing an output signal OUT(N), therefrom. The plurality of stages {SN} is electrically connected to each other in serial such that the first input of the shift register stage SN is electrically connected to the output of the (N-1)-th shift register stage SN-1 for receiving an output signal OUT(N-1) therefrom, the second input of the shift register stage SN is electrically connected to the output of the (N+1)-th shift register stage SN+1 for receiving an output signal OUT(N+1) therefrom, and the output of the shift register stage SN is electrically connected to the first input of the (N+1)-th shift register stage, SN+1 for providing the output signal OUT(N+1) thereto.