Shiftable Memory Atomic Data Shifting
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Solution Overview
Problem
Conventional memory systems face synchronization challenges and inefficiencies when multiple processes or processors concurrently access shared memory, as they rely on external processors for data shifting, leading to proportional time requirements and speed limitations.
Innovation Solution
The implementation of shiftable memory with built-in data shifting capability allows for lateral translation of contiguous data subsets within the memory, enabling atomic operations without external processor resources, thus eliminating the need for data transfer and reducing shifting time to be independent of data length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional memory systems use external processors for data shifting operations, then data can be shifted between locations, but the shifting time is proportional to data length and processing speed is limited
Solution Approach 1:
The memory system performs data shifting operations autonomously using built-in shift registers and control logic, eliminating the need for external processor intervention. The memory controller internally manages the shifting process by generating control signals that operate shift registers directly within the memory array, enabling self-service data manipulation without CPU involvement.
Solution Approach 2:
The patent replaces the mechanical-like sequential processing approach with an parallel hardware-based shifting mechanism. Instead of processing data bits sequentially through software instructions, the system uses hardware shift registers that can shift data in parallel across multiple positions simultaneously, substituting sequential mechanical operations with parallel electrical signal propagation.
2Productivity
If multiple processes concurrently access shared memory, then memory utilization increases, but synchronization problems and race conditions occur
Solution Approach 1:
The system performs preliminary actions by establishing memory regions as atomic before concurrent access occurs. Through memory ordering controls and atomic marker placement, the system pre-defines which memory operations must execute in a specific sequence, ensuring that concurrent processes respect these pre-established boundaries and cannot interfere with each other's atomic operations.
Solution Approach 2:
The patent introduces an intermediary memory control layer that mediates between concurrent processes and shared memory. This control layer includes atomic operation markers, memory barriers, and region management structures that coordinate access between multiple processes, ensuring proper synchronization without requiring complex inter-process communication protocols.
3Device complexity
If data shifting operations are performed externally by the processor, then memory structure remains simple, but processing overhead and latency increase
Solution Approach 1:
The patent merges the data shifting functionality with the memory structure itself by integrating shift registers and control logic directly into the memory array. This combination allows shifting operations to be performed within the memory hardware rather than requiring separate external processing circuits, reducing the number of components while enabling faster operation.
Data Source
AI summary
A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset.