Shifted Array Cell Circuit Structure for IC Yield Evaluation
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Solution Overview
Problem
Current integrated circuit manufacturing processes face inefficiencies due to high costs and time consumption in optimizing processing parameters, as well as delayed detection of abnormalities during wafer fabrication, leading to reduced production yield and the need for additional testing.
Innovation Solution
A circuit structure with a first and second array cell, where the second array cell is shifted a predetermined distance relative to the first, allowing for comparison of electrical characteristics to evaluate yield and adjust processing conditions in real-time, thereby expediting analysis and improving production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional splitting test and DOE are performed after wafer fabrication, then production yield can be evaluated, but abnormality detection is delayed and additional testing time is required
Solution Approach 1:
The patent implements preliminary action by incorporating test circuit structures directly into the wafer before fabrication completes. The first and second array cells are designed with intentional shifts and connected through connecting areas, enabling real-time monitoring of fabrication processes. This allows abnormality detection during fabrication rather than after, eliminating the need for delayed DOE and splitting tests, thus reducing testing time while maintaining yield evaluation capability
Solution Approach 2:
The patent establishes a feedback mechanism by comparing electrical characteristics between the first array cell and second array cell through their connecting areas. The intentional shifting creates measurable differences that provide real-time feedback on fabrication quality. This continuous feedback loop enables immediate detection of process abnormalities and adjustments, replacing the traditional delayed testing approach and reducing overall testing time
2Manufacturing precision
If multiple wafers are used for DOE with different parameters, then processing optimization can be performed, but cost and time consumption increase significantly
Solution Approach 1:
The patent merges multiple testing functions into a single wafer by integrating both the first array cell and second array cell with intentional shifts within the same wafer structure. The connecting areas between cells allow simultaneous measurement of multiple parameters (such as alignment accuracy, dimensional control, and process variations) without requiring separate wafers for each parameter, thus reducing DOE time and cost while maintaining optimization capability
Solution Approach 2:
The test circuit structure designed in the patent serves multiple functions: it evaluates alignment accuracy, measures dimensional control, and monitors process variations all within a single integrated structure. The first and second array cells with intentional shifts can test multiple fabrication parameters simultaneously, making the structure universal and eliminating the need for multiple specialized wafers, thereby reducing both time and cost
3Reliability
If array cells are shifted by intentional misalignment, then process tolerance and yield properties can be evaluated, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the test structure into distinct first array cell and second array cell components, each with specific intentional shifts. The connecting areas are separately designed to link these segments. This modular segmentation allows independent optimization of each cell's shift parameters while maintaining overall test functionality, making the complexity manageable and enabling comprehensive yield property analysis through systematic comparison of segmented structures
Data Source
AI summary
A circuit structure of an integrated circuit is provided. The circuit structure is adapted for a circuit layout of a wafer. The circuit structure at least includes a first array cell and a second array cell. The second array cell and the first array cell are connected to each other and have a connecting area, wherein the second array cell is shifted a distance along the connecting area. Therefore, the result of yield enhancement is achieved.